[PATCH] Only use NO_REGS in cost calculation when !hard_regno_mode_ok for GENERAL_REGS and mode.

r14-172-g0368d169492017 replaces GENERAL_REGS with NO_REGS in cost calculation when the preferred register class are not known yet. It regressed powerpc PR109610 and PR109858, it looks too aggressive to use NO_REGS when mode can be allocated with GENERAL_REGS. The patch takes a step back, still use

Re: [PATCH] RISC-V: Adjust stdint.h to stdint-gcc.h for rvv tests

RISC-V glibc will require corresponding muilti-lib has built there, otherwise will report something like: /usr/include/gnu/stubs.h:11:11: fatal error: gnu/stubs-ilp32d.h: No such file or directory But actually we only require those fixed length types to compile and scan assembly or dump, So we

Re: ping: [PATCH] rs6000: Enable const_anchor for 'addi'

Gentle ping... Jiufu Guo via Gcc-patches writes: > Hi, > > I'm thinking that we may enable this patch for stage1, so ping it. > https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603530.html > > BR, > Jeff (Jiufu) > > Jiufu Guo writes: > >> Hi, >> >> There is a functionality as const_anch

ping^^^ [PATCH] rs6000: mark tieable between INT and FLOAT

Gentle ping... Jiufu Guo via Gcc-patches writes: > Hi, > > I would ping this patch for stage1: > https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609504.html > > BR, > Jeff (Jiufu) > > Jiufu Guo via Gcc-patches writes: > >> Hi, >> >> Gently Ping: >> https://gcc.gnu.org/pipermail/gcc-pat

ping^^: [PATCH V2] rs6000: Enhance lowpart/highpart DI->SF by mtvsrws/mtvsrd

Gentle ping... Jiufu Guo via Gcc-patches writes: > Hi > > I would like to ping this patch for stage1: > https://gcc.gnu.org/pipermail/gcc-patches/2023-February/612168.html > > BR, > Jeff (Jiufu) > > Jiufu Guo writes: > >> Hi, >> >> Compare with previous version: >> https://gcc.gnu.org/pipermail

Re: [PATCH RFC] c-family: make -fno-permissive upgrade pedwarns

On Mon, May 15, 2023 at 3:56 PM Jason Merrill wrote: > > On 5/15/23 03:32, Richard Biener wrote: > > On Fri, May 12, 2023 at 10:54 PM Jason Merrill via Gcc-patches > > wrote: > >> > >> In the context of the recent discussion, it occurred to me that this > >> semantic > >> would be useful, but cu

Re: [PATCH 1/2] vect: Refactor code for index == count in vect_transform_slp_perm_load_1

On Wed, May 17, 2023 at 8:09 AM Kewen.Lin wrote: > > Hi, > > This patch is to refactor the handlings for the case (index > == count) in a loop of vect_transform_slp_perm_load_1, in > order to prepare a subsequent adjustment on *nperm. This > patch doesn't have any functional changes. The diff is

Re: [PATCH] vect: Don't retry if the previous analysis fails

On Wed, May 17, 2023 at 8:06 AM Kewen.Lin wrote: > > Hi, > > When working on a cost tweaking patch, I found that a newly > added test case has different dumpings with stage-1 and > bootstrapped gcc. By looking into it, the apparent reason > is vect_analyze_loop_2 doesn't get slp_done_for_suggeste

Re: [PATCH] Fix PR 106900: array-bounds warning inside simplify_builtin_call

On Wed, May 17, 2023 at 2:54 AM Andrew Pinski via Gcc-patches wrote: > > The problem here is that VRP cannot figure out isize could not be 0 > due to using integer_zerop. This patch removes the use of integer_zerop > and instead checks for 0 directly after converting the tree to > an unsigned HOST

PING^2 [PATCH 0/9] rs6000: Rework rs6000_emit_vector_compare

Hi, Gentle ping this series: https://gcc.gnu.org/pipermail/gcc-patches/2022-November/607146.html BR, Kewen > > on 2022/11/24 17:15, Kewen Lin wrote: >> Hi, >> >> Following Segher's suggestion, this patch series is to rework >> function rs6000_emit_vector_compare for vector float and int >> in

Re: [PATCH] RISC-V: Adjust stdint.h to stdint-gcc.h for rvv tests

> Huh, including stdint-gcc.h looks completely wrong. What's the issue you are > trying to solve? The way I understood it is that that's a temporary workaround until all multilib et al. (+testsuite) configurations are in place but I haven't checked the details myself. Eventually this should be d

PING^1 [PATCH] libgcc: Use initarray section type for .init_stack

Hi, Gentle ping this: https://gcc.gnu.org/pipermail/gcc-patches/2023-March/614228.html BR, Kewen on 2023/3/20 14:33, Kewen.Lin via Gcc-patches wrote: > Hi, > > One of my workmates found there is a warning like: > > libgcc/config/rs6000/morestack.S:402: Warning: ignoring > incorrect sect

Re: [PATCH v2] sched: Change no_real_insns_p to no_real_nondebug_insns_p [PR108273]

Hi, I'd like to gentle ping this patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-March/614818.html BR, Kewen on 2023/3/29 15:18, Kewen.Lin via Gcc-patches wrote: > Hi, > > By addressing Alexander's comments, against v1 this > patch v2 mainly: > > - Rename no_real_insns_p to no_real_no

Re: [PATCH] RISC-V: Adjust stdint.h to stdint-gcc.h for rvv tests

On Tue, May 16, 2023 at 9:11 AM Robin Dapp via Gcc-patches wrote: > > > This patch would like to align the stdint.h to the stdint-gcc.h for all > > the RVV test files. Aka: > > > > stdint.h => stdint-gcc.h > > Looks good. Jeff already pre-approved so you can go ahead and install > this on the tru

[PATCH 2/2] vect: Enhance cost evaluation in vect_transform_slp_perm_load_1

Hi, Following Richi's suggestion in [1], I'm working on deferring cost evaluation next to the transformation, this patch is to enhance function vect_transform_slp_perm_load_1 which could under-cost for vector permutation, since the costing doesn't try to consider nvectors_per_build, it's inconsist

[PATCH] Optimized "(X - N * M) / N + M" to "X / N" if valid

Hi, This patch tries to optimize "(X - N * M) / N + M" to "X / N". As per the discussions in PR108757, we know this transformation is valid only under some conditions. For C code, "/" towards zero (trunc_div), and "X - N * M" maybe wrap/overflow/underflow. So, it is valid that "X - N * M" does not

[PATCH 1/2] vect: Refactor code for index == count in vect_transform_slp_perm_load_1

Hi, This patch is to refactor the handlings for the case (index == count) in a loop of vect_transform_slp_perm_load_1, in order to prepare a subsequent adjustment on *nperm. This patch doesn't have any functional changes. Bootstrapped and regtested on x86_64-redhat-linux, aarch64-linux-gnu and p

[PATCH] vect: Don't retry if the previous analysis fails

Hi, When working on a cost tweaking patch, I found that a newly added test case has different dumpings with stage-1 and bootstrapped gcc. By looking into it, the apparent reason is vect_analyze_loop_2 doesn't get slp_done_for_suggested_uf set expectedly, the following retrying will use the garbag

[PATCH] RISC-V: Introduce rounding mode operand into fixed-point intrinsics

From: Juzhe-Zhong According to new comming fixed-point API: https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222 Introduce vxrm argument: - vint32m1_t __riscv_vsadd_vv_i32m1 (vint32m1_t op1, vint32m1_t op2, size_t vl); + vint32m1_t __riscv_vsadd_vv_i32m1 (vint32m1_t op1, vint32m1_t op2, s

Re: RISC-V: Remove masking third operand of rotate instructions

On 5/10/23 09:50, Jivan Hakobyan via Gcc-patches wrote: Subject: RISC-V: Remove masking third operand of rotate instructions From: Jivan Hakobyan via Gcc-patches Date: 5/10/23, 09:50 To: gcc-patches@gcc.gnu.org Rotate instructions do not need to mask the third operand. For example RV64 th

Re: RISC-V Test Errors and Failures

On 5/16/23 20:39, Palmer Dabbelt wrote: By "chroot environment" you mean something like a debootstrap-into-chroot with qemu-user/binfmt-misc?  I don't have that setup right now, but it wouldn't be a big lift. Essentially, yes. I actually have a home built ones for the various targets. T

Re: RISC-V Test Errors and Failures

On 5/16/23 21:33, Kito Cheng via Gcc-patches wrote: diff --git a/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run b/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run index 94d6ec5..efc3a80 100755 --- a/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run +++ b/scripts/wrapper/qemu/riscv64-un

Re: Re: [PATCH V5] RISC-V: Using merge approach to optimize repeating sequence in vec_init

On Wed, May 17, 2023 at 11:36 AM juzhe.zh...@rivai.ai wrote: > > >> Does it means we assume inner_int_mode is DImode? (because sizeof > >> (uint64_t)) > >> or it should be something like `for (unsigned int i = 0; i < > >> (GET_MODE_SIZE(inner_int_mode ()) * 8 / npatterns ()); i++)` ? > No, sizeof

Re: Re: [PATCH V5] RISC-V: Using merge approach to optimize repeating sequence in vec_init

>> Does it means we assume inner_int_mode is DImode? (because sizeof (uint64_t)) >> or it should be something like `for (unsigned int i = 0; i < >> (GET_MODE_SIZE(inner_int_mode ()) * 8 / npatterns ()); i++)` ? No, sizeof (uint64_t) means uint64_t mask = 0; >> Do you mind give more comment about t

Re: RISC-V Test Errors and Failures

> diff --git a/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run > b/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run > index 94d6ec5..efc3a80 100755 > --- a/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run > +++ b/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run > @@ -12,4 +12,4 @@ done >

Re: [PATCH V5] RISC-V: Using merge approach to optimize repeating sequence in vec_init

> + > +/* Get the mask for merge approach. > + > + Consider such following case: > + {a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b} > + To merge "a", the mask should be 1010 > + To merge "b", the mask should be 0101 > +*/ > +rtx > +rvv_builder::get_merge_mask_bitfield (u

Re: RISC-V Test Errors and Failures

On Tue, 16 May 2023 20:08:26 PDT (-0700), Vineet Gupta wrote: On 5/16/23 19:53, Palmer Dabbelt wrote: Probably, I'll go try and bump stuff and see if it works... Word of caution: Best to not disturb your existing setup, a try a fresh checkout first Even easier, I think I can get away with

Re: RISC-V Test Errors and Failures

On 5/16/23 19:53, Palmer Dabbelt wrote: Probably, I'll go try and bump stuff and see if it works... Word of caution: Best to not disturb your existing setup, a try a fresh checkout first

Re: [PATCH] RISC-V: Add rounding mode enum for fixed-point intrinsics

I would like to defer this until the PR has updated. On Wed, May 17, 2023 at 9:52 AM wrote: > > From: Juzhe-Zhong > > Hi, since fixed-point with modeling rounding mode intrinsics are coming: > https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222 > > I am adding vxrm rounding mode enum to

Re: RISC-V Test Errors and Failures

On Tue, 16 May 2023 19:51:48 PDT (-0700), Patrick O'Neill wrote: On 5/16/23 19:47, Palmer Dabbelt wrote: On Tue, 16 May 2023 19:46:28 PDT (-0700), Vineet Gupta wrote: On 5/16/23 19:21, Kito Cheng wrote: Palmer: For short-term, this should help your internal test: https://github.com/riscv-col

Re: RISC-V Test Errors and Failures

On 5/16/23 19:47, Palmer Dabbelt wrote: On Tue, 16 May 2023 19:46:28 PDT (-0700), Vineet Gupta wrote: On 5/16/23 19:21, Kito Cheng wrote: Palmer: For short-term, this should help your internal test: https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1233 That only helps if using blee

Re: RISC-V Test Errors and Failures

On Tue, 16 May 2023 19:46:28 PDT (-0700), Vineet Gupta wrote: On 5/16/23 19:21, Kito Cheng wrote: Palmer: For short-term, this should help your internal test: https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1233 That only helps if using bleeding edge toolchain scripts (which I regula

Re: RISC-V Test Errors and Failures

On 5/16/23 19:21, Kito Cheng wrote: Palmer: For short-term, this should help your internal test: https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1233 That only helps if using bleeding edge toolchain scripts (which I regularly do and so did Patrick). Palmer has a fork of toolchain s

Re: RISC-V Test Errors and Failures

On Tue, 16 May 2023 19:32:21 PDT (-0700), jeffreya...@gmail.com wrote: On 5/16/23 20:05, Palmer Dabbelt wrote: On Tue, 16 May 2023 19:00:12 PDT (-0700), Jeff Law wrote: On 5/16/23 19:29, Palmer Dabbelt wrote: I think the most pressing need is bleeding edge gcc regression tracking.   @Je

Re: RISC-V Test Errors and Failures

On 5/16/23 20:05, Palmer Dabbelt wrote: On Tue, 16 May 2023 19:00:12 PDT (-0700), Jeff Law wrote: On 5/16/23 19:29, Palmer Dabbelt wrote: I think the most pressing need is bleeding edge gcc regression tracking.   @Jeff is anything setup on sourceware and/or usable ? I thought they do h

Re: Re: RISC-V Test Errors and Failures

Palmer: For short-term, this should help your internal test: https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1233 On Wed, May 17, 2023 at 10:20 AM Kito Cheng wrote: > > Currently we are highly rely on simulator can setup correctly by ELF > attribute or -march setting, but seems not true

Re: Re: RISC-V Test Errors and Failures

Currently we are highly rely on simulator can setup correctly by ELF attribute or -march setting, but seems not true for everyone, for longer term we need something like check_effective_target_aarch64_sve_hw, but as Palmer point out, we might need...bunch of that for different extensions On We

Re: [PATCH V4 2/2] rs6000: use li;x?oris to build constant

Hi, On 2023-05-15 14:53, Kewen.Lin wrote: Hi Jeff, on 2022/12/12 09:38, Jiufu Guo wrote: Hi, For constant C: If '(c & 0xULL) == 0x' or say: 32(1) || 1(0) || 15(x) || 16(0), we could use "lis; xoris" to build. Here N(M) means N continuous bit M, x for M means i

Re: Re: RISC-V Test Errors and Failures

On Tue, 16 May 2023 19:07:01 PDT (-0700), juzhe.zh...@rivai.ai wrote: Oh, I see. Kito has add /* { dg-do run { target { riscv_vector } } } */ But not all RVV tests has use this and I not sure whether it can work. I think Kito can answer it. If yes, I think we should add all of them. Unless I'm

Re: RISC-V Test Errors and Failures

On 5/16/23 20:08, Vineet Gupta wrote: I think the most pressing need is bleeding edge gcc regression tracking.   @Jeff is anything setup on sourceware and/or usable ? I thought they do have existing bots for some arches to spin up build / run - perhaps runs are native and not qemu. IIRC J

Re: RISC-V Test Errors and Failures

On 5/16/23 18:29, Palmer Dabbelt wrote: On Tue, 16 May 2023 18:04:37 PDT (-0700), Vineet Gupta wrote: + Christoph, Jiawei On 5/16/23 17:20, Palmer Dabbelt wrote: We really need to add some CI around RV toolchains to trip on these sooner ! Sounds like you're volunteering to set one up? P

Re: Re: RISC-V Test Errors and Failures

Oh, I see. Kito has add /* { dg-do run { target { riscv_vector } } } */ But not all RVV tests has use this and I not sure whether it can work. I think Kito can answer it. If yes, I think we should add all of them. Thanks. juzhe.zh...@rivai.ai From: Andrew Pinski Date: 2023-05-17 10:02 To: juzh

Re: RISC-V Test Errors and Failures

On Tue, 16 May 2023 19:00:12 PDT (-0700), Jeff Law wrote: On 5/16/23 19:29, Palmer Dabbelt wrote: I think the most pressing need is bleeding edge gcc regression tracking.   @Jeff is anything setup on sourceware and/or usable ? I thought they do have existing bots for some arches to spin up

Re: RISC-V Test Errors and Failures

On Tue, May 16, 2023 at 6:58 PM juzhe.zh...@rivai.ai wrote: > > Hi, Palmer. > I saw your patch showed there are a lot of run time fail (execution fail) of > C++. > bug-*.C > > These tests are RVV api intrinsics tests coming from Kito's that I have > already fixed all of them. > I just double che

Re: RISC-V Test Errors and Failures

On 5/16/23 19:29, Palmer Dabbelt wrote: I think the most pressing need is bleeding edge gcc regression tracking.   @Jeff is anything setup on sourceware and/or usable ? I thought they do have existing bots for some arches to spin up build / run - perhaps runs are native and not qemu. IIRC

RISC-V Test Errors and Failures

Hi, Palmer. I saw your patch showed there are a lot of run time fail (execution fail) of C++. bug-*.C These tests are RVV api intrinsics tests coming from Kito's that I have already fixed all of them. I just double checked again they all passed. I think it may be your regression environment does

[PATCH] RISC-V: Add rounding mode enum for fixed-point intrinsics

From: Juzhe-Zhong Hi, since fixed-point with modeling rounding mode intrinsics are coming: https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222 I am adding vxrm rounding mode enum to user first before the API intrinsic. This patch is simple && obvious. Ok for trunk ? gcc/ChangeLog:

Re: RISC-V Test Errors and Failures

On Tue, 16 May 2023 18:04:37 PDT (-0700), Vineet Gupta wrote: + Christoph, Jiawei On 5/16/23 17:20, Palmer Dabbelt wrote: We really need to add some CI around RV toolchains to trip on these sooner ! Sounds like you're volunteering to set one up? Patrick's github CI patch seems to be a great

Re: RISC-V Test Errors and Failures

+ Christoph, Jiawei On 5/16/23 17:20, Palmer Dabbelt wrote: We really need to add some CI around RV toolchains to trip on these sooner ! Sounds like you're volunteering to set one up? Patrick's github CI patch seems to be a great start. Lets wait for it to get merged, that will at least ca

[PATCH] Fix PR 106900: array-bounds warning inside simplify_builtin_call

The problem here is that VRP cannot figure out isize could not be 0 due to using integer_zerop. This patch removes the use of integer_zerop and instead checks for 0 directly after converting the tree to an unsigned HOST_WIDE_INT. This allows VRP to figure out isize is not 0 and `isize - 1` will alw

Re: RISC-V Test Errors and Failures

On Tue, 16 May 2023 17:16:11 PDT (-0700), Vineet Gupta wrote: On 5/16/23 16:06, Palmer Dabbelt wrote: A few of us were talking about test-related issues in the patchwork meeting this morning.  I bumped to trunk and did a full rebuild, I'm getting the following (it's in riscv-systems-ci/riscv-gnu

Re: RISC-V Test Errors and Failures

On 5/16/23 16:06, Palmer Dabbelt wrote: A few of us were talking about test-related issues in the patchwork meeting this morning.  I bumped to trunk and did a full rebuild, I'm getting the following (it's in riscv-systems-ci/riscv-gnu-toolchain).  This is about what I remember seeing last time

[committed] c: Remove restrictions on declarations in 'for' loops for C2X

C2X removes a restriction that the only declarations in the declaration part of a 'for' loop are declarations of objects with storage class auto or register. Implement this change, making the diagnostics into pedwarn_c11 calls instead of errors (as usual for features added in a new standard versio

RISC-V Test Errors and Failures

A few of us were talking about test-related issues in the patchwork meeting this morning. I bumped to trunk and did a full rebuild, I'm getting the following (it's in riscv-systems-ci/riscv-gnu-toolchain). This is about what I remember seeing last time I ran the tests, which was a week or so ago

Re: [PATCH] aarch64: Add SVE instruction types

Hi, Kyrill. It makes sense. I could add the classification to a different attribute as you did and keep it in aarch64 as well. I took the same approach, gleaning over several optimization guides for Arm processors supporting SVE and figuring out the smallest number of types that could cover m

Re: [PATCH] configure: Implement --enable-host-pie

Hi Marek, > On 16 May 2023, at 16:29, Marek Polacek via Gcc-patches > wrote: > > Ping. I’m trying this on Darwin (since I have a local patch to do this for modern [darwin20+] versions, which do not allow non-PIE) I think you are missing a hunk to deal with Ada. thanks for the patch Iain >

Re: [PATCH] s390: Implement TARGET_ATOMIC_ALIGN_FOR_MODE

On 5/16/23 08:43, Stefan Schulze Frielinghaus wrote: > So far atomic objects are aligned according to their default alignment. > For 128 bit scalar types like int128 or long double this results in an > 8 byte alignment which is wrong and must be 16 byte. > > libstdc++ already computes a correct al

Re: [PATCH] c++: Don't try to initialize zero width bitfields in zero initialization [PR109868]

On 5/16/23 15:34, Jakub Jelinek wrote: Hi! My GCC 12 change to avoid removing zero-sized bitfields as they are important for ABI and are needed for layout compatibility traits apparently causes zero sized bitfields to be initialized in the IL, which at least in 13+ results in ICEs in the ranger

Re: [PATCH] c++: -Wdangling-reference not suppressed in template [PR109774]

On 5/16/23 15:13, Marek Polacek wrote: In check_return_expr, we suppress the -Wdangling-reference warning when we're sure it would be a false positive. It wasn't working in a template, though, because the suppress_warning call was never reached. Bootstrapped/regtested on x86_64-pc-linux-gnu, ok

[PATCH] c++: Don't try to initialize zero width bitfields in zero initialization [PR109868]

Hi! My GCC 12 change to avoid removing zero-sized bitfields as they are important for ABI and are needed for layout compatibility traits apparently causes zero sized bitfields to be initialized in the IL, which at least in 13+ results in ICEs in the ranger which is upset about zero precision types

[PATCH] c++: -Wdangling-reference not suppressed in template [PR109774]

In check_return_expr, we suppress the -Wdangling-reference warning when we're sure it would be a false positive. It wasn't working in a template, though, because the suppress_warning call was never reached. Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk and 13.2? PR c++/1097

[committed] libstdc++: Disable cacheline alignment for DJGPP [PR109741]

Tested powerpc64le-linux. Builds OK on djgpp too. Pushed to trunk. -- >8 -- DJGPP (and maybe other targets) uses MAX_OFILE_ALIGNMENT=16 which means that globals (and static objects) can't have alignment greater than 16. This causes an error for the locks defined in src/c++11/shared_ptr.cc becaus

[PATCH] libstdc++: Disable embedded tzdata for all 16-bit targets

Tested powerpc64le-linux. Builds OK for avr too. Roger, does this work for xstormy16? -- >8 -- libstdc++-v3/ChangeLog: * acinclude.m4 (GLIBCXX_ZONEINFO_DIR): Extend logic for avr and msp430 to all 16-bit targets. * configure: Regenerate. --- libstdc++-v3/acinclude.m4 |

[committed] rs6000: Enable REE pass by default

rs6000: Enable REE pass by default Add ree pass as a default pass for rs6000 target for O2 and above. 2023-05-16 Ajit Kumar Agarwal gcc/ChangeLog: * common/config/rs6000/rs6000-common.cc: Add REE pass as a default rs6000 target pass for O2 and above. * doc/invoke.texi

[committed gcc13 backport] RISCV: Inline subword atomic ops

On 5/15/23 21:32, Jeff Law wrote: On 5/9/23 10:01, Patrick O'Neill wrote: Ping. OK for backporting.  Sorry for the delay. jeff Committed. Thanks, Patrick

Re: [PATCH] c++: desig init in presence of list ctor [PR109871]

On 5/16/23 11:38, Patrick Palka wrote: add_list_candidates has logic to reject designated initialization of a non-aggregate type, but this is inadvertendly being suppressed if the type has a list constructor due to the order of case analysis, which in the below testcase leads to us incorrectly tr

RE: [PATCH v3] Machine_Mode: Extend machine_mode from 8 to 16 bits

Update the PATCH v4 (I am sorry, missed the v4 in subject) as below with x86 bootstrap test passed. https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618742.html Pan -Original Message- From: Gcc-patches On Behalf Of Li, Pan2 via Gcc-patches Sent: Tuesday, May 16, 2023 8:17 PM To: Ric

[PATCH] c++: desig init in presence of list ctor [PR109871]

add_list_candidates has logic to reject designated initialization of a non-aggregate type, but this is inadvertendly being suppressed if the type has a list constructor due to the order of case analysis, which in the below testcase leads to us incorrectly treating the list initializer as an ordinar

[PATCH] configure: Implement --enable-host-bind-now

As promised in the --enable-host-pie patch, this patch adds another configure option, --enable-host-bind-now, which adds -z now when linking the compiler executables in order to extend hardening. BIND_NOW with RELRO allows the GOT to be marked RO; this prevents GOT modification attacks. This opti

[PATCH] Machine_Mode: Extend machine_mode from 8 to 16 bits

From: Pan Li We are running out of the machine_mode(8 bits) in RISC-V backend. Thus we would like to extend the machine_mode bit size from 8 to 16 bits. However, it is sensitive to extend the memory size in common structure like tree or rtx. This patch would like to extend the machine_mode bits t

[committed] RISC-V: Fix wrong select_kind in riscv_compute_multilib

Seems like I screw up bare-metal toolchian multi lib selection during finxing linux multi-lib selction... gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_compute_multilib): Fix wrong select_kind... --- gcc/common/config/riscv/riscv-common.cc | 6 +++--- 1 file changed

Re: [PATCH] configure: Implement --enable-host-pie

Ping. On Tue, May 09, 2023 at 03:41:58PM -0400, Marek Polacek via Gcc-patches wrote: > [ This is my third attempt to add this configure option. The first > version was approved but it came too late in the development cycle. > The second version was also approved, but I had to revert it: >

Re: [PATCH v5 1/4] rs6000: Enable REE pass by default

Hi! On Tue, May 16, 2023 at 11:45:28AM +0530, Ajit Agarwal wrote: > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -12455,8 +12455,8 @@ Attempt to remove redundant extension instructions. > This is especially > helpful for the x86-64 architecture, which implicitly zero-extends in 64

[PATCH] OpenMP: Array shaping operator and strided "target update" for C

Following the similar support for C++ and Fortran, here is the C implementation for the OpenMP 5.0 array-shaping operator, and for strided and rectangular updates for "target update" directives. Much of the implementation is shared with the previously-posted C++ support: https://gcc.gnu.org/pip

Support parallel testing in libgomp: fallback Perl 'flock' [PR66005]

Hi! On 2023-05-05T10:59:31+0200, I wrote: > On 2023-05-05T10:55:41+0200, I wrote: >> [Putting Bernhard, Honza, Segher in CC, as they are eager to test this, >> based on recent comments on IRC.] ;-P >> First, establish the parallel testing infrastructure -- while still >> hard-coding the number

Remove stale Autoconf checks for Perl

Hi! OK to push the attached "Remove stale Autoconf checks for Perl"? For avoidance of doubt, there still exist a few instances of Perl usage in the GCC build process (like, when 'contrib/make_sunver.pl' is used), but those always directly invoke 'perl'. As this, apparently, is working fine, I'm

Re: [PATCH] RFC: New compact syntax for insn and insn_split in Machine Descriptions

On 24/04/2023 09:33, Richard Sandiford via Gcc-patches wrote: Richard Sandiford writes: Tamar Christina writes: Hi All, This patch adds support for a compact syntax for specifying constraints in instruction patterns. Credit for the idea goes to Richard Earnshaw. I am sending up this RFC to

[GCC12 backport] arm: MVE testsuite and backend bugfixes

Hi all, We've recently sent up a lot of patches overhauling the testsuite of the Arm MVE backend. With these changes, we've also identified and fixed a number of bugs (some backend bugs and many to do with the polymorphism of intrinsics in MVE the header file). These would all be relevant to

Re: [PATCH v4 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces.

On 29/04/23 5:03 am, Jeff Law wrote: > > > On 4/28/23 16:42, Hans-Peter Nilsson wrote: >> On Sat, 22 Apr 2023, Ajit Agarwal via Gcc-patches wrote: >> >>> Hello All: >>> >>> This new version of patch 4 use improve ree pass for rs6000 target using >>> defined ABI interfaces. >>> Bootstrapped an

Re: [PATCH] rtl: AArch64: New RTL for ABD

Sorry for the slow reply. Oluwatamilore Adebayo writes: > From afa416dab831795f7e1114da2fb9e94ea3b8c519 Mon Sep 17 00:00:00 2001 > From: oluade01 > Date: Fri, 14 Apr 2023 15:10:07 +0100 > Subject: [PATCH 2/4] AArch64: New RTL for ABD > > This patch adds new RTL and tests for sabd and uabd > > PR

RE: [PATCH v3] Machine_Mode: Extend machine_mode from 8 to 16 bits

Thanks Richard Sandiford for review. Yes, currently the class access_info will be extended from 8 bytes to 12 bytes, which is missed in the table. With the adjustment as you suggested it will be 8 bytes but unfortunately the change of m_kind may trigger some ICE in some test case(s). I will ta

Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab]

Tejas Belagod writes: >>> + { >>> + b = build3 (BIT_FIELD_REF, TREE_TYPE (f.lhs), val, >>> + bitsize_int (step * BITS_PER_UNIT), >>> + bitsize_int ((16 - step) * BITS_PER_UNIT)); >>> + >>> + return gimple_build_assign (f.lhs, b); >>> +

Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab]

From: Richard Sandiford Date: Tuesday, May 16, 2023 at 2:15 PM To: Tejas Belagod Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH] [PR96339] AArch64: Optimise svlast[ab] Tejas Belagod writes: >> + { >> +int i; >> +int nelts = vector_cst_encoded_nelts (v); >> +int first_el = 0; >>

Re: Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer

Hi, Richard. Forget about V10 patch. Just go directly V11 patch. I am so sorry that I send V10 since I originally did not notice Case 2 and Case 3 are totally the same. I apologize for that. I have reviewed V11 patch twice, it seems that this patch is much more reasonable and better understanding

Re: [PATCH 0/7] openmp: OpenMP 5.1 loop transformation directives

On Tue, May 16, 2023 at 11:45:16AM +0200, Frederik Harwath wrote: > The place where different compilers implement the loop transformations > was discussed in an OpenMP loop transformation meeting last year. Two > compilers (another one and GCC with this patch series) transformed the loops > in the

[PATCH] aarch64: Allow moves after tied-register intrinsics (2nd edition)

I missed these two in g:4ff89f10ca0d41f9cfa76 because I was testing on a system that didn't support big-endian compilation. Testing on aarch64_be-elf shows no other related failures (although the overall results are worse than for little-endian). Tested on aarch64_be-elf & pushed. Richard gcc/t

Re: Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer

Hi, Richard and Richi. I am so sorry for sending you garbage patches (My mistake, sending RISC-V patches to you). I finally realize that Case 2 and Case 3 are totally the same sequence! I have combined them into single function called "vect_adjust_loop_lens_control" I have sent V11 patch: https:

[PATCH V11] VECT: Add decrement IV support in Loop Vectorizer

From: Ju-Zhe Zhong This patch implement decrement IV for length approach in loop control. Address comment from kewen that incorporate the implementation inside "vect_set_loop_controls_directly" instead of a standalone function. Address comment from Richard using MIN_EXPR to handle these 3 follo

[PATCH V2] RISC-V: Add FRM and rounding mode operand into floating point intrinsics

From: Juzhe-Zhong This patch is adding rounding mode operand and FRM_REGNUM dependency into floating-point instructions. The floating-point instructions we added FRM and rounding mode operand: 1. vfadd/vfsub 2. vfwadd/vfwsub 3. vfmul 4. vfdiv 5. vfwmul 6. vfwmacc/vfwnmacc/vfwmsac/vfwnmsac 7. vfs

[PATCH V2] RISC-V: Add FRM and rounding mode operand into floating point intrinsics

From: Juzhe-Zhong This patch is adding rounding mode operand and FRM_REGNUM dependency into floating-point instructions. The floating-point instructions we added FRM and rounding mode operand: 1. vfadd/vfsub 2. vfwadd/vfwsub 3. vfmul 4. vfdiv 5. vfwmul 6. vfwmacc/vfwnmacc/vfwmsac/vfwnmsac 7. vfs

Re: [PATCH 0/7] openmp: OpenMP 5.1 loop transformation directives

Hi Jakub, On 15.05.23 12:19, Jakub Jelinek wrote: On Fri, Mar 24, 2023 at 04:30:38PM +0100, Frederik Harwath wrote: this patch series implements the OpenMP 5.1 "unroll" and "tile" constructs. It includes changes to the C,C++, and Fortran front end for parsing the new constructs and a new middl

Re: Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer

Hi, Richard. I have sent V10: https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618718.html I can't combine implementation Case 2 and Case 3, Case 2 each control (len) are coming from same rgc. But Case 3 each control (len) are coming coming from different rgc. Can you help me with that ? Also,

Re: [PATCH] Add auto-resizing capability to irange's [PR109695]

On 5/15/23 20:14, Aldy Hernandez wrote: On 5/15/23 17:07, Aldy Hernandez wrote: On 5/15/23 12:42, Jakub Jelinek wrote: On Mon, May 15, 2023 at 12:35:23PM +0200, Aldy Hernandez wrote: gcc/ChangeLog: PR tree-optimization/109695 * value-range.cc (irange::operator=): Resize range.    

[PATCH V10] VECT: Add decrement IV support in Loop Vectorizer

From: Ju-Zhe Zhong This patch implement decrement IV for length approach in loop control. Address comment from kewen that incorporate the implementation inside "vect_set_loop_controls_directly" instead of a standalone function. Address comment from Richard using MIN_EXPR to handle these 3 follo

[committed 2/3] libstdc++: Stop using _GLIBCXX_USE_C99_STDINT_TR1 in

Tested powerpc64le-linux. Pushed to trunk. -- >8 -- The _GLIBCXX_USE_C99_STDINT_TR1 macro (and the comments about it in acinclude.m4 and config.h) are misleading when it is also used for , not only . It is also wrong, because the configure checks for TR1 use -std=c++98 and a target might define u

[committed 3/3] libstdc++: Stop using TR1 macros in and

Tested powerpc64le-linux. Pushed to trunk. -- >8 -- As with the two commits before this, the _GLIBCXX_USE_C99_CTYPE_TR1 and _GLIBCXX_USE_C99_FENV_TR1 macros are misleading when they are also used for and , not only for TR1 headers. It is also wrong, because the configure checks for TR1 use -std=

[committed 1/3] libstdc++: Stop using _GLIBCXX_USE_C99_COMPLEX_TR1 in

Tested powerpc64le-linux. Pushed to trunk. -- >8 -- The _GLIBCXX_USE_C99_COMPLEX_TR1 macro (and the comments about it in acinclude.m4 and config.h) are misleading when it is also used for , not only . It is also wrong, because the configure checks for TR1 use -std=c++98 and a target might define

Re: [PATCH v3] Machine_Mode: Extend machine_mode from 8 to 16 bits

pan2...@intel.com writes: > diff --git a/gcc/rtl-ssa/accesses.h b/gcc/rtl-ssa/accesses.h > index c5180b9308a..38b4d6160c2 100644 > --- a/gcc/rtl-ssa/accesses.h > +++ b/gcc/rtl-ssa/accesses.h > @@ -254,7 +254,7 @@ private: >unsigned int m_spare : 2; > >// The value returned by the accessor

[committed] libstdc++: Add assertion to debug_allocator test

Tested x86_64-linux. Pushed to trunk. -- >8 -- libstdc++-v3/ChangeLog: * testsuite/ext/debug_allocator/check_deallocate_null.cc: Add assertion to ensure expected exception is throw. --- .../testsuite/ext/debug_allocator/check_deallocate_null.cc | 3 ++- 1 file changed, 2 ins

[committed] libstdc++: Require tzdb support for chrono::zoned_time printer test

Tested powerpc64le-linux. Pushed to trunk. -- >8 -- libstdc++-v3/ChangeLog: * testsuite/libstdc++-prettyprinters/chrono.cc: Only test printer for chrono::zoned_time for cx11 ABI and tzdb effective target. --- libstdc++-v3/testsuite/libstdc++-prettyprinters/chrono.cc | 3

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