On Thu, Jul 29, 2021 at 4:38 PM Andrew MacLeod wrote:
>
> On 7/29/21 3:19 AM, Richard Biener wrote:
> > On Wed, Jul 28, 2021 at 4:39 PM Andrew MacLeod wrote:
> >>
> >> Which has removed the second call to builtin_abort()(Even before we
> >> get to EVRP!)
> >>
> >> SO the issue doesn't seem to
On 7/29/21 4:38 PM, Jason Merrill wrote:
On 7/29/21 3:50 AM, Jakub Jelinek wrote:
Hi!
The following patch attempts to implement the compiler helpers for
libstdc++ std::is_pointer_interconvertible_base_of trait and
std::is_pointer_interconvertible_with_class template function.
For the former __
on 2021/7/29 下午4:01, Richard Biener wrote:
> On Fri, Jul 23, 2021 at 10:41 AM Kewen.Lin wrote:
>>
>> on 2021/7/22 下午8:56, Richard Biener wrote:
>>> On Tue, Jul 20, 2021 at 4:37
>>> PM Kewen.Lin wrote:
Hi,
This v2 has addressed some review comments/suggestions:
- Us
On 7/29/21 10:21 AM, Jakub Jelinek wrote:
On Thu, Jul 29, 2021 at 09:50:10AM +0200, Jakub Jelinek via Gcc-patches wrote:
Now that I'm writing the above text and rereading the
pointer-interconvertibility definition, I think my first_nonstatic_data_member_p
and fold_builtin_is_pointer_inverconvert
Ping again.
On Sun, 2021-07-11 at 01:48 +0800, Xi Ruoyao wrote:
> We are comparing enum values (in wide_int) to check ODR violation.
> However, if we compare two wide_int values with different precision,
> we'll trigger an assert, leading to ICE. With enum-base introduced
> in C++11, it's easy to
Ping again.
On Wed, 2021-06-23 at 11:11 +0800, Xi Ruoyao wrote:
> Commit message shamelessly copied from 1777beb6b129 by jakub:
>
> This function, because it is sometimes called even outside of function
> bodies, uses create_tmp_var_raw rather than create_tmp_var. But in
> order
> for that to wo
Ping again.
On Mon, 2021-06-21 at 21:42 +0800, Xi Ruoyao wrote:
> Middle-end started to emit vec_cmp and vec_cmpu since GCC 11, causing
> ICE on MIPS with MSA enabled. Add the pattern to prevent it.
>
> Bootstrapped and regression tested on mips64el-linux-gnu.
> Ok for trunk?
>
> gcc/
>
>
An old itch being scratched: the documentation lies; it's not "the
number of registers used as operands", unless the target makes a
special arrangement to that effect, and there's nothing in the guts of
gcc setting up or assuming those semantics.
Instead, see calls.c:expand_call, variable next_arg
This bug made me dive into some of the murkier waters of gcc, namely
the source of operand 2 to the "call" pattern. It can be pretty
poisonous, but is unused (either directly or later) by most targets.
The target function_arg (and function_incoming_arg), can unless
specially handled, cause a VOID
On Thu, 29 Jul 2021, 23:44 Hans-Peter Nilsson, wrote:
> Commit r12-2534 was incomplete and (by inspection derived from
> an MMIX build) failing for targets without an insn for
> compare_and_swap for pointer-size objects, IOW for targets for
> which "ATOMIC_POINTER_LOCK_FREE != 2" is true:
>
> x/g
Commit r12-2534 was incomplete and (by inspection derived from
an MMIX build) failing for targets without an insn for
compare_and_swap for pointer-size objects, IOW for targets for
which "ATOMIC_POINTER_LOCK_FREE != 2" is true:
x/gcc/libstdc++-v3/src/c++17/memory_resource.cc: In member function
'
Hello, gentle maintainer.
This is a message from the Translation Project robot.
A revised PO file for textual domain 'gcc' has been submitted
by the German team of translators. The file is available at:
https://translationproject.org/latest/gcc/de.po
(This file, 'gcc-11.2.0.de.po', has jus
From: Andrew Pinski
So I was looking at some older PRs (PR 16016 in this case),
I noticed that some of the testcases were removed when
the tree-ssa branch was merged. This adds them back in.
OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.
Thanks,
Andrew Pinski
gcc/testsuit
On Tue, Jul 27, 2021 at 10:29:13PM -0400, David Edelsohn via Gcc-patches wrote:
> > Add a naive implementation of the subject x86 intrinsic to
> > ease porting.
> >
> > 2021-07-15 Paul A. Clarke
> >
> > gcc
> > * config/rs6000/smmintrin.h (_mm_minpos_epu16): New.
>
> Segher already appr
On Thu, Jul 29, 2021 at 08:02:43PM +, Qing Zhao wrote:
> This is the 7th version of the patch for the new security feature for GCC.
> I have tested it with bootstrap on both x86 and aarch64, regression testing
> on both x86 and aarch64.
> Also compile CPU2017 (running is ongoing), without any
On Thu, 29 Jul 2021, Hongtao Liu via Gcc-patches wrote:
> > Rather than using FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 whenever TARGET_SSE2
> > (i.e. whenever the type is available), it might make more sense to follow
> > AArch64 and use it only when the hardware instructions are available. In
> > any
On Tue, 27 Jul 2021, Hongtao Liu via Gcc-patches wrote:
> modified gcc/emit-rtl.c
> @@ -928,6 +928,10 @@ validate_subreg (machine_mode omode, machine_mode imode,
> fix them all. */
>if (omode == word_mode)
> ;
> + /* ???Similarly like (subreg:DI (reg:SF), also allow (subreg:SI (
On 7/29/21 3:50 AM, Jakub Jelinek wrote:
Hi!
The following patch attempts to implement the compiler helpers for
libstdc++ std::is_pointer_interconvertible_base_of trait and
std::is_pointer_interconvertible_with_class template function.
For the former __is_pointer_interconvertible_base_of trait
On Thu, Jul 29, 2021 at 8:54 PM Palmer Dabbelt wrote:
>
> On Tue, 27 Jul 2021 02:32:12 PDT (-0700), cmuell...@gcc.gnu.org wrote:
> > Ok, so if I understand correctly Palmer and Andrew prefer
> > overlap_op_by_pieces to be controlled
> > by its own field in the riscv_tune_param struct and not by th
On 7/29/21 5:28 AM, Jakub Jelinek wrote:
On Wed, Jul 28, 2021 at 04:32:08PM -0400, Jason Merrill wrote:
As the following testcase shows, we don't parse properly
C++11 attribute-declaration:
https://eel.is/c++draft/dcl.dcl#nt:attribute-declaration
cp_parser_toplevel_declaration just handles empt
On Thu, 29 Jul 2021 11:44:09 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
ping
On Wed, Jul 21, 2021 at 5:28 PM Kito Cheng wrote:
This patch set allow target to use customized multi-lib mechanism rather than
the built-in
multi-lib mechanism.
The motivation of this patch is RISC-V might have v
The branch-on-bit patterns have been disabled since the transition away
from cc0 on the H8. This patch reinstates them. This tends to be a
fairly nice win since the bit test is 2 or 4 bytes, but the
and-with-constant approaches is going to be 2-6 bytes or worse if the
input value doesn't die.
On Tue, 27 Jul 2021 02:32:12 PDT (-0700), cmuell...@gcc.gnu.org wrote:
Ok, so if I understand correctly Palmer and Andrew prefer
overlap_op_by_pieces to be controlled
by its own field in the riscv_tune_param struct and not by the field
slow_unaligned_access in this struct
(i.e. slow_unaligned_acc
ping
On Wed, Jul 21, 2021 at 5:28 PM Kito Cheng wrote:
>
> This patch set allow target to use customized multi-lib mechanism rather than
> the built-in
> multi-lib mechanism.
>
> The motivation of this patch is RISC-V might have very complicated multi-lib
> re-use
> rule*, which is hard to main
On Linux/x86_64,
2e96b5f14e4025691b57d2301d71aa6092ed44bc is the first bad commit
commit 2e96b5f14e4025691b57d2301d71aa6092ed44bc
Author: Aldy Hernandez
Date: Tue Jun 15 12:32:51 2021 +0200
Backwards jump threader rewrite with ranger.
caused
FAIL: gcc.dg/tree-prof/20050826-2.c scan-tree-
This patch resolves the failure of powerpc64 long double complex divide
in native ibm long double format after the patch "Practical improvement
to libgcc complex divide".
The new code uses the following macros which are intended to be mapped
to appropriate values according to the underlying hardwa
On 7/22/21 7:15 PM, Sergei Trofimovich wrote:
From: Sergei Trofimovich
r12-1804 ("cp: add support for per-location warning groups.") among other
things removed warning suppression from a few places including ptrmemfuncs.
Currently ptrmemfuncs don't have valid BINFO attached which causes ICEs
i
Hi,
This patch adds a check to make_frontend_typeinfo to generate a stub
Object class if one doesn't exist in the run-time library.
Having a stub will prevent errors from occuring when compiling D code
with an empty object.d. Though if it were to actually be used
implicitly then an error should
Hi,
C++ constructors return void, even though the D front-end semantic
treats them as implicitly returning `this'. To handle this correctly,
the object reference is cached and used as the result of the expression.
Bootstrapped and regression tested on x86_64-linux-gnu/-mx32/-m32,
committed to ma
Hi,
When casting from bool, the result is either 0 or 1, any other value
violates @safe code, so enforce that it is never invalid.
This patch does that by lowering rvalue reads into `(bool & 1)'.
Bootstrapped and regression tested on x86_64-linux-gnu/-mx32/-m32,
committed to mainline, and backpo
Hi,
This patch adds a clean-up for removing any generated DI header files
created before semantic analysis was ran.
If an error occurs later during compilation, remember that we generated
the headers, so that they can be removed before exit.
Bootstrapped and regression tested on x86_64-linux-gnu
Hi,
This patch prepares the escape_d_format function to handle being given a
quoted string. Something that the self-hosted D front-end does with a
new format helper for symbols.
If the format string is enclosed by two '`' characters, then don't
escape the first and laster characters.
There are
> -Original Message-
> From: Prathamesh Kulkarni
> Sent: 29 July 2021 15:45
> To: Kyrylo Tkachov
> Cc: gcc Patches ; Richard Earnshaw
>
> Subject: Re: [ARM] PR66791: Replace builtins in vld1
>
> On Thu, 29 Jul 2021 at 14:57, Kyrylo Tkachov
> wrote:
> >
> > Hi Prathamesh,
> >
> > > --
On Thu, 29 Jul 2021 at 14:57, Kyrylo Tkachov wrote:
>
> Hi Prathamesh,
>
> > -Original Message-
> > From: Prathamesh Kulkarni
> > Sent: 26 July 2021 22:24
> > To: gcc Patches ; Kyrylo Tkachov
> > ; Richard Earnshaw
> >
> > Subject: [ARM] PR66791: Replace builtins in vld1
> >
> > Hi,
> >
On 7/29/21 2:26 AM, Andrew Burgess wrote:
* Martin Sebor [2021-07-28 10:16:59 -0600]:
On 7/28/21 5:14 AM, Andrew Burgess wrote:
* Martin Sebor via Gcc-patches [2021-07-19 09:08:35
-0600]:
On 7/17/21 2:36 PM, Jan-Benedict Glaw wrote:
Hi Martin!
On Fri, 2021-06-04 15:27:04 -0600, Martin S
On 7/29/21 3:19 AM, Richard Biener wrote:
On Wed, Jul 28, 2021 at 4:39 PM Andrew MacLeod wrote:
Which has removed the second call to builtin_abort()(Even before we
get to EVRP!)
SO the issue doesn't seem to be removing the divide by 0, it seems to be
a pattern match for [0,1] that is trig
The RISC-V cpymemsi expansion is called, whenever the by-pieces
infrastructure will not be taking care of the builtin expansion.
Currently, that's the case for e.g. memcpy() with n <= 24 bytes.
The code emitted by the by-pieces infrastructure emits code, that
performs unaligned accesses if the targ
Hi,
The attached patch replaces builtins in vld1_dup intrinsics with call
to corresponding vdup_n intrinsic and removes entry for vld1_dup from
arm_neon_builtins.def.
Bootstrapped+tested on arm-linux-gnueabihf.
OK to commit ?
Thanks,
Prathamesh
gcc/ChangeLog:
PR target/66791
* con
On Thu, Jul 29, 2021 at 09:50:10AM +0200, Jakub Jelinek via Gcc-patches wrote:
> Now that I'm writing the above text and rereading the
> pointer-interconvertibility definition, I think my
> first_nonstatic_data_member_p
> and fold_builtin_is_pointer_inverconvertible_with_class have one bug,
> for
2021-07-28 Bill Schmidt
gcc/
* config/rs6000/rs6000-call.c (rs6000_debug_type): New function.
(def_builtin): Change debug formatting for easier parsing and
include more information.
(rs6000_init_builtins): Add dump of autogenerated builtins.
(altivec_init
2021-06-17 Bill Schmidt
gcc/
* config/rs6000/rs6000-call.c (rs6000_expand_new_builtin): New
forward decl.
(rs6000_invalid_new_builtin): New stub function.
(rs6000_expand_builtin): Call rs6000_expand_new_builtin.
(rs6000_expand_ldst_mask): New stub functio
2021-07-27 Bill Schmidt
gcc/
* config/rs6000/rs6000-builtin-new.def (ASSEMBLE_ACC): Add mmaint
flag.
(ASSEMBLE_PAIR): Likewise.
(BUILD_ACC): Likewise.
(DISASSEMBLE_ACC): Likewise.
(DISASSEMBLE_PAIR): Likewise.
(PMXVBF16GER2): Likewise.
Create a new version of this function that uses the new infrastructure,
and particularly checks for supported builtins the new way.
2021-07-28 Bill Schmidt
gcc/
* config/rs6000/rs6000-call.c (rs6000_new_builtin_decl): New
function.
(rs6000_builtin_decl): Call it.
---
g
2021-07-19 Bill Schmidt
gcc/testsuite/
* gcc.target/powerpc/bfp/scalar-extract-exp-2.c: Adjust.
* gcc.target/powerpc/bfp/scalar-extract-sig-2.c: Adjust.
* gcc.target/powerpc/bfp/scalar-insert-exp-2.c: Adjust.
* gcc.target/powerpc/bfp/scalar-insert-exp-5.c: Adjust
2021-03-05 Bill Schmidt
gcc/
* config/rs6000/rs6000-call.c (new_cpu_expand_builtin):
Implement.
---
gcc/config/rs6000/rs6000-call.c | 100
1 file changed, 100 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000
2021-03-04 Bill Schmidt
gcc/
* config/rs6000/rs6000-call.c (rs6000-builtins.h): New #include.
(rs6000_init_builtins): Call rs6000_autoinit_builtins; skip the old
initialization logic when new builtins are enabled.
---
gcc/config/rs6000/rs6000-call.c | 12
1
On Tue, Jul 13, 2021 at 9:24 AM H.J. Lu wrote:
>
> On Tue, Jul 13, 2021 at 8:41 AM Joseph Myers wrote:
> >
> > On Tue, 13 Jul 2021, H.J. Lu wrote:
> >
> > > On Mon, Jul 12, 2021 at 8:59 PM Wang, Pengfei
> > > wrote:
> > > >
> > > > > Return _Float16 and _Complex _Float16 values in %xmm0/%xmm1 r
2021-06-17 Bill Schmidt
gcc/
* config/rs6000/rs6000-call.c (new_mma_expand_builtin):
Implement.
---
gcc/config/rs6000/rs6000-call.c | 103
1 file changed, 103 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000
2021-07-28 Bill Schmidt
gcc/
* config/rs6000/rs6000-call.c (new_htm_spr_num): New function.
(new_htm_expand_builtin): Implement.
(rs6000_expand_new_builtin): Handle 32-bit and endian cases.
---
gcc/config/rs6000/rs6000-call.c | 202
1 fi
2021-03-05 Bill Schmidt
gcc/
* config/rs6000/rs6000.c (rs6000-builtins.h): New include.
(rs6000_new_builtin_vectorized_function): New function.
(rs6000_new_builtin_md_vectorized_function): Likewise.
(rs6000_builtin_vectorized_function): Call
rs6000_new_bu
2021-04-01 Bill Schmidt
gcc/
* config/rs6000/rs6000-builtin-new.def: Add power8-vector stanza.
---
gcc/config/rs6000/rs6000-builtin-new.def | 438 +++
1 file changed, 438 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def
b/gcc/config/rs6000/rs600
2021-03-05 Bill Schmidt
gcc/
* config/rs6000/rs6000-gen-builtins.c (write_init_file):
Initialize new_builtins_are_live to 1.
---
gcc/config/rs6000/rs6000-gen-builtins.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c
2021-07-28 Bill Schmidt
gcc/
* config/rs6000/rs6000-call.c (elemrev_icode): Implement.
(ldv_expand_builtin): Likewise.
(lxvrse_expand_builtin): Likewise.
(lxvrze_expand_builtin): Likewise.
(stv_expand_builtin): Likewise.
---
gcc/config/rs6000/rs6000-call
It seems quite strange for these to be "vector long" for 64-bit and
"vector long long" for 32-bit, when "vector long long" will do for both.
2021-03-04 Bill Schmidt
gcc/
* config/rs6000/rs6000-call.c (rs6000_init_builtins): Change
initialization of V2DI_type_node and unsigned_V
2021-07-28 Bill Schmidt
gcc/
* config/rs6000/altivec.h: Delete a number of #defines that are
now superfluous; alphabetize; include rs6000-vecdefines.h; include
some synonyms.
---
gcc/config/rs6000/altivec.h | 519 +++-
1 file changed, 38
There are a few leftover places where we use the old rs6000_builtins_decl
array, but we need to use rs6000_builtins_decl_x instead when the new
builtins infrastructure is in play.
2021-07-28 Bill Schmidt
gcc/
* config/rs6000/rs6000.c (rs6000_builtin_reciprocal): Use
rs6000_buil
2021-03-05 Bill Schmidt
gcc/
* config/rs6000/rs6000-call.c (rs6000_invalid_new_builtin):
Implement.
(rs6000_expand_ldst_mask): Likewise.
(rs6000_init_builtins): Initialize altivec_builtin_mask_for_load.
---
gcc/config/rs6000/rs6000-call.c | 101 +
2021-03-24 Bill Schmidt
gcc/
* config/rs6000/rs6000-call.c (rs6000_init_builtins): Remove
TARGET_EXTRA_BUILTINS guard.
---
gcc/config/rs6000/rs6000-call.c | 51 -
1 file changed, 24 insertions(+), 27 deletions(-)
diff --git a/gcc/config/rs6000/r
This is another patch that looks bigger than it really is. Because we
have a new namespace for the builtins, allowing us to have both the old
and new builtin infrastructure supported at once, we need versions of
these functions that use the new builtin namespace. Otherwise the code is
unchanged.
Although this patch looks quite large, the changes are fairly minimal.
Most of it is duplicating the large function that does the overload
resolution using the automatically generated data structures instead of
the old hand-generated ones. This doesn't make the patch terribly easy to
review, unfor
2021-03-04 Bill Schmidt
gcc/
* config/rs6000/darwin.h (SUBTARGET_INIT_BUILTINS): Use the new
decl when new_builtins_are_live.
* config/rs6000/rs6000-builtin-new.def (__builtin_cfstring): New
built-in.
---
gcc/config/rs6000/darwin.h | 8 ++--
gc
2021-06-07 Bill Schmidt
gcc/
* config/rs6000/rs6000-builtin-new.def: Add cell stanza.
---
gcc/config/rs6000/rs6000-builtin-new.def | 27
1 file changed, 27 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def
b/gcc/config/rs6000/rs6000-builtin-
2021-06-16 Bill Schmidt
gcc/
* config/rs6000/rs6000-builtin-new.def: Add mma stanza.
---
gcc/config/rs6000/rs6000-builtin-new.def | 416 +++
1 file changed, 416 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def
b/gcc/config/rs6000/rs6000-builtin-
2021-06-15 Bill Schmidt
gcc/
* config/rs6000/rs6000-builtin-new.def: Add ieee128-hw, dfp,
crypto, and htm stanzas.
---
gcc/config/rs6000/rs6000-builtin-new.def | 215 +++
1 file changed, 215 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.de
2021-07-28 Bill Schmidt
gcc/
* config/rs6000/rs6000-builtin-new.def: Add power10 and power10-64
stanzas.
---
gcc/config/rs6000/rs6000-builtin-new.def | 523 +++
1 file changed, 523 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def
b/gcc/c
2021-06-10 Bill Schmidt
gcc/
* config/rs6000/rs6000-call.c (rs6000_init_builtins): Initialize
various pointer type nodes.
* config/rs6000/rs6000.h (rs6000_builtin_type_index): Add enum
values for various pointer types.
(ptr_V16QI_type_node): New macro.
2021-06-15 Bill Schmidt
gcc/
* config/rs6000/rs6000-builtin-new.def: Add power9-vector, power9,
and power9-64 stanzas.
---
gcc/config/rs6000/rs6000-builtin-new.def | 375 +++
1 file changed, 375 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-ne
2021-04-02 Bill Schmidt
gcc/
* config/rs6000/rs6000-builtin-new.def: Add power7 and power7-64
stanzas.
---
gcc/config/rs6000/rs6000-builtin-new.def | 39
1 file changed, 39 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def
b/gcc/conf
2021-06-07 Bill Schmidt
gcc/
* config/rs6000/rs6000-builtin-new.def: Add always, power5, and
power6 stanzas.
---
gcc/config/rs6000/rs6000-builtin-new.def | 72
1 file changed, 72 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def
b/gc
2021-06-07 Bill Schmidt
gcc/
* config/rs6000/rs6000-builtin-new.def: Add vsx stanza.
---
gcc/config/rs6000/rs6000-builtin-new.def | 857 +++
1 file changed, 857 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def
b/gcc/config/rs6000/rs6000-builtin-
2021-06-10 Bill Schmidt
gcc/
* config/rs6000/rs6000-builtin-new.def: Finish altivec stanza.
* config/rs6000/rs6000-call.c (rs6000_init_builtins): Move
initialization of pcvoid_type_node here...
(altivec_init_builtins): ...from here.
* config/rs6000/rs6000
2021-06-07 Bill Schmidt
gcc/
* config.gcc (target_gtfiles): Add ./rs6000-builtins.h.
* config/rs6000/t-rs6000 (EXTRA_GTYPE_DEPS): Set.
---
gcc/config.gcc | 1 +
gcc/config/rs6000/t-rs6000 | 1 +
2 files changed, 2 insertions(+)
diff --git a/gcc/config.gcc b/gcc/con
Differences from previous version:
- Removed the change to add rs6000-c.o to extra_objs (unnecessary)
- Avoided race condition and documented how this works
2021-07-27 Bill Schmidt
gcc/
* config.gcc (powerpc*-*-*): Add rs6000-builtins.o to extra_objs.
* config/rs6000/rs6000-g
Hi!
Original patch series here:
https://gcc.gnu.org/pipermail/gcc-patches/2021-April/568840.html
V2 patch series here:
https://gcc.gnu.org/pipermail/gcc-patches/2021-June/572231.html
V3 patch series here:
https://gcc.gnu.org/pipermail/gcc-patches/2021-June/573020.html
Thanks for all the reviews
David: PING
Le lundi 19 juillet 2021 à 12:10 -0400, Antoni Boucher a écrit :
> I'm sending the patch once again for review/approval.
>
> I fixed the doc to use the new function names.
>
> Le vendredi 18 juin 2021 à 16:37 -0400, David Malcolm a écrit :
> > On Fri, 2021-06-18 at 15:41 -0400, Anton
On 7/28/21 4:21 PM, will schmidt wrote:
On Thu, 2021-06-17 at 10:19 -0500, Bill Schmidt via Gcc-patches wrote:
+/* Vector compares; EQ, NE, GE, GT, LE. */
+case RS6000_BIF_VCMPEQUB:
+case RS6000_BIF_VCMPEQUH:
+case RS6000_BIF_VCMPEQUW:
+case RS6000_BIF_VCMPEQUD:
+ fo
Hi!
After recent libstdc++ header changes no longer includes
(parts of?) and doesn't have to and no longer includes
(parts of?) .
This patch fixes:
testsuite/g++.dg/pr71389.C:10:39: error: aggregate 'std::array, 16> v13' has incomplete type and cannot be defined
as well as
testsuite/g++.dg/cpp0
On 29/07/2021 08:34, Richard Biener wrote:
On Wed, Jul 28, 2021 at 3:04 PM Andrew Stubbs wrote:
This patch follows up my previous patch and supports more variants of
LLVM 12.
There are still other incompatibilities with LLVM 12, but this at least
the ELF attributes should now automatically tu
Now backported to devel/omp/gcc-11.
Andrew
On 28/07/2021 14:03, Andrew Stubbs wrote:
This patch follows up my previous patch and supports more variants of
LLVM 12.
There are still other incompatibilities with LLVM 12, but this at least
the ELF attributes should now automatically tune to any
On 29.07.21 09:09, Jakub Jelinek wrote:
On Thu, Jul 29, 2021 at 12:56:32AM +0200, Jakub Jelinek wrote:
On Wed, Jul 28, 2021 at 01:22:53PM +0200, Tobias Burnus wrote:
gfortran.dg/dg.exp: Add libgfortran as -I flag for ISO*.h [PR101305]
Wouldn't it be better to do that in gcc/testsuite/lib/gfort
On Wed, Jul 28, 2021 at 04:32:08PM -0400, Jason Merrill wrote:
> > As the following testcase shows, we don't parse properly
> > C++11 attribute-declaration:
> > https://eel.is/c++draft/dcl.dcl#nt:attribute-declaration
> >
> > cp_parser_toplevel_declaration just handles empty-declaration parsing
>
Hi Prathamesh,
> -Original Message-
> From: Prathamesh Kulkarni
> Sent: 26 July 2021 22:24
> To: gcc Patches ; Kyrylo Tkachov
> ; Richard Earnshaw
>
> Subject: [ARM] PR66791: Replace builtins in vld1
>
> Hi,
> Similar to aarch64, this patch replaces call to builtin by
> dereferencing __
Hi,
The Neon subtract-long/subract-widen instructions can select the top
or bottom half of the operand registers. This selection does not
change the cost of the underlying instruction and this should be
reflected by the RTL cost function.
This patch adds RTL tree traversal in the Neon subtract co
Hi,
The Neon add-long/add-widen instructions can select the top or bottom
half of the operand registers. This selection does not change the
cost of the underlying instruction and this should be reflected by
the RTL cost function.
This patch adds RTL tree traversal in the Neon add cost function to
* Martin Sebor [2021-07-28 10:16:59 -0600]:
> On 7/28/21 5:14 AM, Andrew Burgess wrote:
> > * Martin Sebor via Gcc-patches [2021-07-19
> > 09:08:35 -0600]:
> >
> > > On 7/17/21 2:36 PM, Jan-Benedict Glaw wrote:
> > > > Hi Martin!
> > > >
> > > > On Fri, 2021-06-04 15:27:04 -0600, Martin Sebor
On Fri, Jul 23, 2021 at 10:41 AM Kewen.Lin wrote:
>
> on 2021/7/22 下午8:56, Richard Biener wrote:
> > On Tue, Jul 20, 2021 at 4:37
> > PM Kewen.Lin wrote:
> >>
> >> Hi,
> >>
> >> This v2 has addressed some review comments/suggestions:
> >>
> >> - Use "!=" instead of "<" in function operator!= (c
Hi!
The following patch attempts to implement the compiler helpers for
libstdc++ std::is_pointer_interconvertible_base_of trait and
std::is_pointer_interconvertible_with_class template function.
For the former __is_pointer_interconvertible_base_of trait that checks first
whether base and derived
Hi Julian!
On 2021-03-02T04:20:11-0800, Julian Brown wrote:
> This patch implements worker-partitioning support in the middle end,
> [...]
I've first separately pushed the mostly "mechanical changes" re
"[OpenACC] Extract 'pass_oacc_loop_designation' out of
'pass_oacc_device_lower'" to master br
On Tue, Jul 27, 2021 at 4:11 AM Kewen.Lin wrote:
>
> on 2021/7/24 上午12:10, Martin Sebor wrote:
> > On 7/23/21 2:35 AM, Kewen.Lin wrote:
> >> Hi,
> >>
> >> Comparing to v2, this v3 removed the new CTOR with struct loops *loops
> >> as Richi clarified. I'd like to support it in a separated follow u
This patch gets rid of the unspecs we were using for the vector merge
instruction and replaces it with generic rtx.
gcc/ChangeLog:
* config/s390/s390-modes.def: Add more vector modes to support
concatenation of two vectors.
* config/s390/s390-protos.h (s390_expand_merge_pe
gcc/ChangeLog:
* config/s390/vector.md (V_HW_64): Remove mode iterator.
(*vec_load_pair): Use V_HW_2 instead of V_HW_64.
* config/s390/vx-builtins.md
(vec_scatter_element_SI): Use V_HW_2 instead of
V_HW_64.
---
gcc/config/s390/vector.md | 7 +++
g
The patch gets rid of the unspec used for the vector permute double
immediate instruction and replaces it with generic rtx.
gcc/ChangeLog:
* config/s390/s390.md (UNSPEC_VEC_PERMI): Remove constant
definition.
* config/s390/vector.md (*vpdi1, *vpdi4): New pattern
de
This patchset, after some prep work, provides an initial
implementation of the TARGET_VECTORIZE_VEC_PERM_CONST hook for IBM Z.
Only the vmrh, vmrl, and vpdi instruction are exploited so far. More
instructions will be added with follow-on patches.
Bootstrapped and regression tested on s390x.
As e
This patch makes use of the vector permute double immediate
instruction for constant permute vectors.
gcc/ChangeLog:
* config/s390/s390.c (expand_perm_with_vpdi): New function.
(vectorize_vec_perm_const_1): Call expand_perm_with_vpdi.
* config/s390/vector.md (*vpdi1, @vpdi
This patch implements the TARGET_VECTORIZE_VEC_PERM_CONST in the IBM Z
backend. The initial implementation only exploits the vector merge
instruction but there is more to come.
gcc/ChangeLog:
* config/s390/s390.c (MAX_VECT_LEN): Define macro.
(struct expand_vec_perm_d): Define str
On Wed, Jul 28, 2021 at 3:04 PM Andrew Stubbs wrote:
>
> This patch follows up my previous patch and supports more variants of
> LLVM 12.
>
> There are still other incompatibilities with LLVM 12, but this at least
> the ELF attributes should now automatically tune to any LLVM 9, 10, or
> 12 assemb
On Wed, 28 Jul 2021, Bernd Edlinger wrote:
> On 7/28/21 2:51 PM, Richard Biener wrote:
> > On Mon, 26 Jul 2021, Bernd Edlinger wrote:
> >
> >> Ignored functions decls that are compiled at the start of
> >> the assembly have bogus line numbers until the first .file
> >> directive, as reported in P
On Wed, Jul 28, 2021 at 4:39 PM Andrew MacLeod wrote:
>
> So Im seeing what appears to me to be inconsistent behaviour.
>
> in pr96094.c we see:
>
> int
> foo (int x)
> {
>if (x >= 2U)
> return 34;
>return 34 / x;
> }
>
> x has a range of [0,1] and since / 0 in undefined, the expecta
On Thu, Jul 29, 2021 at 12:56:32AM +0200, Jakub Jelinek wrote:
> On Wed, Jul 28, 2021 at 01:22:53PM +0200, Tobias Burnus wrote:
> > gfortran.dg/dg.exp: Add libgfortran as -I flag for ISO*.h [PR101305]
> >
> > gcc/testsuite/
> > PR libfortran/101305
> > * gfortran.dg/dg.exp: Add '-I /libgfo
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