Hi,
After Martin's commit r271338, we now emit quotes around reserved
names, and some tests started to fail on aarch64 and arm.
This should fix them, OK?
Christophe
2019-05-20 Christophe Lyon
* gcc.target/aarch64/target_attr_10.c: Add quotes to expected
error message.
On Fri, 17 May 2019 at 11:24, Richard Biener wrote:
>
>
> Bootstrap / testing in progress on x86_64-unknown-linux-gnu.
>
> Richard.
>
> 2019-05-17 Richard Biener
>
> c/
> * gimple-parser.c (c_parser_gimple_statement): Handle __VEC_PERM.
> (c_parser_gimple_unary_expressio
On 5/17/19 10:24 PM, Jonathan Wakely wrote:
On 17/05/19 18:19 +0200, François Dumont wrote:
Hi
I got tired of '__n' being used in _Hashtable for many different
purposes: node, bucket, bucket count, bucket hint. It makes the code
difficult to read. This code makes sure that __n is a node e
Hi
std::deque is supposed to be like a double-queue that you can attack
from front and back. But currrently its implementation makes it behave
differently when starting from a fresh deque. If push_back then all goes
well, it is copy/move to the current internal 'node'. If push_front then
a
This replaces "wH" by "v", "wI" by "d", and when both are allowed it
uses "wa"; all with isa "p8v".
2019-05-19 Segher Boessenkool
* config/rs6000/constraints.md (define_register_constraint "wH"):
Delete.
(define_register_constraint "wI"): Delete.
* config/rs600
This replaces the "wy" constraint by "wa", with isa "p8v". It also
creates a new attribute , used together with all .
2019-05-19 Segher Boessenkool
* config/rs6000/constraints.md (define_register_constraint "wy"):
Delete.
* config/rs6000/rs6000.h (enum r6000_reg_class
This replaces the "wu" constraint by "v", with isa "p8v". Or, in most
cases, use "wa", since the instructions allow all VSX registers, and it
does not change how GCC behaves, so it is clearer that way.
This also delete the unused .
2019-05-19 Segher Boessenkool
* config/rs6000/const
This replaces the "wb" constraint by "v", with isa "p9v".
2019-05-19 Segher Boessenkool
* config/rs6000/constraints.md (define_register_constraint "wb"):
Delete.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
RS6000_CONSTRAINT_wb.
* config
This replaces the "wo" constraint by "wa", with isa "p9v".
2019-05-19 Segher Boessenkool
* config/rs6000/constraints.md (define_register_constraint "wo"):
Delete.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
RS6000_CONSTRAINT_wo.
* confi
This replaces "wJ" by "wI", and "wK by "wH", both with isa "p9v".
2019-05-19 Segher Boessenkool
* config/rs6000/constraints.md (define_register_constraint "wJ"):
Delete.
(define_register_constraint "wK"): Delete.
* config/rs6000/rs6000.h (enum r6000_reg_class_e
This is the first batch of patches using the "enabled" and "isa"
attributes. Tested on Power7 powerpc64-linux {-m32,-m64}, and on
Power9 powerpc64le-linux. Committing to trunk.
Segher
Segher Boessenkool (6):
rs6000: Delete the "wo" constraint
rs6000: Delete the "wb" constraint
rs6000: D
CWG 2094 partially reverts CWG 496, which means that volatile-qualified scalars
are, once again, trivially copyable; [basic.types] now says "Scalar types,
trivially copyable class types, arrays of such types, and cv-qualified
versions of these types are collectively called trivially copyable types.
On Sun, May 19, 2019 at 01:00:45PM -0700, Andrew Pinski wrote:
> On Sun, May 19, 2019 at 12:54 PM Segher Boessenkool
> wrote:
> >
> > On Sun, May 19, 2019 at 03:21:01PM -0400, Marek Polacek wrote:
> > > On Sun, May 19, 2019 at 03:11:08AM -0500, Segher Boessenkool wrote:
> > > > On Sun, May 19, 201
On Sun, May 19, 2019 at 12:54 PM Segher Boessenkool
wrote:
>
> On Sun, May 19, 2019 at 03:21:01PM -0400, Marek Polacek wrote:
> > On Sun, May 19, 2019 at 03:11:08AM -0500, Segher Boessenkool wrote:
> > > On Sun, May 19, 2019 at 09:35:45AM +0200, Martin Liška wrote:
> > > > Do we really need a comm
On Sun, May 19, 2019 at 03:21:01PM -0400, Marek Polacek wrote:
> On Sun, May 19, 2019 at 03:11:08AM -0500, Segher Boessenkool wrote:
> > On Sun, May 19, 2019 at 09:35:45AM +0200, Martin Liška wrote:
> > > Do we really need a commit integer numbers after the transition? I know
> > > we're used to i
On Sun, May 19, 2019 at 9:26 PM Steve Kargl
wrote:
>
> On Sun, May 19, 2019 at 09:10:57PM +0300, Janne Blomqvist wrote:
> > On Sun, May 19, 2019 at 7:15 PM Steve Kargl
> > wrote:
> > >
> > > On Sun, May 19, 2019 at 01:40:59PM +0300, Janne Blomqvist wrote:
> > > >
> > > > +#if defined(HAVE_SIGACTI
On Mai 19 2019, Marek Polacek wrote:
> On Sun, May 19, 2019 at 03:11:08AM -0500, Segher Boessenkool wrote:
>> On Sun, May 19, 2019 at 09:35:45AM +0200, Martin Liška wrote:
>> > Do we really need a commit integer numbers after the transition? I know
>> > we're used to it.
>> > But git commit hash
On Sun, May 19, 2019 at 03:11:08AM -0500, Segher Boessenkool wrote:
> On Sun, May 19, 2019 at 09:35:45AM +0200, Martin Liška wrote:
> > Do we really need a commit integer numbers after the transition? I know
> > we're used to it.
> > But git commit hash provides that same.
>
> Revision numbers ar
First, my apologies for not responding five days ago. Joseph's mail
issued as I was transitioning to a new machine and the day before I
spent some hours in the ER of my local hospital, and I missed it in
the confusion.
In case you missed it on the main list, git-svn is *not safe* for
histories wit
On Sun, May 19, 2019 at 09:10:57PM +0300, Janne Blomqvist wrote:
> On Sun, May 19, 2019 at 7:15 PM Steve Kargl
> wrote:
> >
> > On Sun, May 19, 2019 at 01:40:59PM +0300, Janne Blomqvist wrote:
> > >
> > > +#if defined(HAVE_SIGACTION) && defined(HAVE_WAITPID)
> > > + static bool sig_init_saved
On Sun, May 19, 2019 at 7:15 PM Steve Kargl
wrote:
>
> On Sun, May 19, 2019 at 01:40:59PM +0300, Janne Blomqvist wrote:
> >
> > +#if defined(HAVE_SIGACTION) && defined(HAVE_WAITPID)
> > + static bool sig_init_saved;
> > + bool sig_init = __atomic_load_n (&sig_init_saved, __ATOMIC_RELAXED
Hello, gentle maintainer.
This is a message from the Translation Project robot.
A revised PO file for textual domain 'gcc' has been submitted
by the Swedish team of translators. The file is available at:
https://translationproject.org/latest/gcc/sv.po
(This file, 'gcc-9.1.0.sv.po', has jus
Hello,
dropping the builtin as early as possible seems like it can only help us
optimize the code. Jakub suggested in the PR that he liked this approach
better than using __builtin_shuffle in the header. There is already some
coverage in the testsuite (as I noticed when I tried to restrict the
I committed the following to update my email address.
Peter
* MAINTAINERS: Update my email address.
Index: MAINTAINERS
===
--- MAINTAINERS (revision 271381)
+++ MAINTAINERS (revision 271382)
@@ -286,7 +286,7 @@ loop optimize
Hello,
this patch lets the test match q_10, which can happen if you modify gcc a
bit... It seems better to me to improve the test now, but if you think it
is better that I wait until I have a gcc patch that actually requires it,
that's fine with me as well.
gcc/testsuite/
2019-05-20 Marc G
Hello,
I noticed this one with BIT_NOT_EXPR a while ago. C++ testcase because I
haven't looked at gimplefe yet...
2019-05-20 Marc Glisse
gcc/
* match.pd (~(vec?cst1:cst2)); New transformation.
gcc/testsuite/
* g++.dg/tree-ssa/cprop-vcond.C
--
Marc GlisseIndex: gcc/match.p
Hello,
2 pieces:
- the first one handles the case where the denominator is negative. It
doesn't happen often with exact_div, so I don't handle it everywhere, but
this one looked trivial
- handle the case where a pointer difference is cast to an unsigned type
before being compared to a const
On Sun, May 19, 2019 at 01:40:59PM +0300, Janne Blomqvist wrote:
>
> +#if defined(HAVE_SIGACTION) && defined(HAVE_WAITPID)
> + static bool sig_init_saved;
> + bool sig_init = __atomic_load_n (&sig_init_saved, __ATOMIC_RELAXED);
> + if (!sig_init)
> + {
> + struct sigactio
I have confirmed that the IDT Winchip 2 does not expressly set %ecx
after a call to cpuid() with %eax = 1, and this causes incorrect
reporting of cpu capabilities. The %ecx register should return 0x0
(and likely %ebx should too) on this hardware. This patch proposes a
fix.
The symptoms of this aro
On Sun, May 19, 2019 at 10:26:54AM +0200, Thomas Koenig wrote:
> Hi Steve,
>
> > Looks good to me. I wonder if we should add a reference
> > to the option that can produce C prototypes for a Fortran
> > procedure in the description of -fbroken-caller.
>
> Thanks, I added a reference to that opti
> On Fri, 17 May 2019, Jan Hubicka wrote:
>
> > Hi,
> > this patch cuts walks in aliasing_component_refs_p if the type we look for
> > can not fit into a given type by comparing their sizes. Similar logic
> > already exists in indirect_ref_may_alias_decl_p.
> >
> > When we walk reference a.b.c.d.
Hi Dominique,
> On 19 May 2019, at 15:10, Dominique d'Humières wrote:
>
> AFAICT the syntax for dg-require-ifunc seems to be
>
> /* { dg-require-ifunc "" } */
>
> with two sets of exceptions:
>
> (1) gcc.target/i386/pr90500-*.c
>
> which explains
>
> FAIL: gcc.target/i386/pr90500-1.c (test
AFAICT the syntax for dg-require-ifunc seems to be
/* { dg-require-ifunc "" } */
with two sets of exceptions:
(1) gcc.target/i386/pr90500-*.c
which explains
FAIL: gcc.target/i386/pr90500-1.c (test for errors, line 6)
FAIL: gcc.target/i386/pr90500-1.c (test for warnings, line 6)
FAIL: gcc.tar
I'm getting this crash on riscv:
/daten/riscv64/gcc/gcc-20190518/Build/./gcc/gccgo
-B/daten/riscv64/gcc/gcc-20190518/Build/./gcc/ -B/usr/riscv64-suse-linux/bin/
-B/usr/riscv64-suse-linux/lib/ -isystem /usr/riscv64-suse-linux/include
-isystem /usr/riscv64-suse-linux/sys-include -O2 -g -I . -c
-
When using posix_spawn or fork to launch a child process, the parent
needs to wait for the child, otherwise the dead child is left as a
zombie process. For this purpose one can install a signal handler for
SIGCHLD.
2019-05-19 Janne Blomqvist
PR libfortran/90038
* intrinsics/exe
Thank you.
What can I do to ensure this gets back-ported as further back as possible? I
assume that it can go all the way back to gcc 7 branch.
Best regards,
Dragan
From: Jeff Law
Sent: Friday, May 17, 2019 6:28 PM
To: Dragan Mladjenovic; gcc-patches@gcc.gn
Hi Paul,
s:PR fortran/90948:PR fortran/90498:g
TIA
Dominique
Hi Steve,
Looks good to me. I wonder if we should add a reference
to the option that can produce C prototypes for a Fortran
procedure in the description of -fbroken-caller.
Thanks, I added a reference to that option (see attached patch).
Committed as r271376.
Regards
Thomas
Index: C
On Sun, May 19, 2019 at 09:35:45AM +0200, Martin Liška wrote:
> Do we really need a commit integer numbers after the transition? I know
> we're used to it.
> But git commit hash provides that same.
Revision numbers are nice short text strings, and from a revision number
you can see approximately
Richard Biener writes:
> This adds, incrementally ontop of moving VEC_PERM_EXPR folding
> to match.pd (but not incremental patch - sorry...), folding
> of single-element insert permutations to BIT_INSERT_EXPR.
>
> Things are quite awkward with the new poly-int vec-perm stuff
> so effectively this
On 5/17/19 2:39 PM, Jakub Jelinek wrote:
On Fri, May 17, 2019 at 02:22:47PM +0200, Martin Liška wrote:
On 5/17/19 1:06 AM, Joseph Myers wrote:
That repository
represents what I consider the collaboratively built consensus on such
things as the desired author map (including handling of the ambig
On 5/17/19 4:59 PM, Maxim Kuvyrkov wrote:
On May 17, 2019, at 3:22 PM, Martin Liška wrote:
On 5/17/19 1:06 AM, Joseph Myers wrote:
That repository
represents what I consider the collaboratively built consensus on such
things as the desired author map (including handling of the ambiguous
author
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