Ping?
thanks,
Cong
On Wed, Mar 19, 2014 at 11:39 AM, Cong Hou wrote:
> On Tue, Mar 18, 2014 at 4:43 AM, Richard Biener wrote:
>>
>> On Mon, 17 Mar 2014, Cong Hou wrote:
>>
>> > On Mon, Mar 17, 2014 at 6:44 AM, Richard Biener wrote:
>> > > On Fri, 14 Mar 2014, Cong Hou wrote:
>> > >
>> > >> O
This patch is fixing PR60656. Elements in a vector with
vect_used_by_reduction property cannot be reordered if the use chain
with this property does not have the same operation.
Bootstrapped and tested on a x86-64 machine.
OK for trunk?
thanks,
Cong
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
Hi All,
This patch enables LRA by default for MIPS. The classic reload is still
available and can be enabled via -mreload switch.
All regression are fixed, with one exception described below.
There was a necessary change in the LRA core as I believe there was a genuine
unhandled case in LRA wh
> > Actually after some additional invetstigation I decided to commit this
> > patch. fixup_noreturn_call already cares about the return value but
> > differently than the new Jakub's code.
>
> Thanks for the quick fix, I confirm that the ACATS failures are all gone.
>
> So we're left with the G
The following patch fixes PR60697. The details of the PR can be
found on
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60697
The patch was successfully bootstrapped and tested on x86-64 and aarch64.
Committed as rev. 208926.
2014-03-28 Vladimir Makarov
PR target/60697
On Fri, Mar 28, 2014 at 2:46 PM, Joseph S. Myers
wrote:
> If you build an x86_64 toolchain with --with-arch enabling various
> instruction set extensions by default, this causes some tests to fail
> that aren't expecting those extensions to be enabled. This patch
> fixes various tests failing lik
Hi,
Revision 201326 fixes a shrink-wrap bug which is also a regression
on 4.8 branch. This patch backports it to 4.8 branch. OK for 4.8
branch.
I also include a testcase for PR rtl-optimization/60700. OK for
trunk and 4.8 branch?
Thanks.
H.J.
--
gcc/
PR rtl-optimization/60700
If you build an x86_64 toolchain with --with-arch enabling various
instruction set extensions by default, this causes some tests to fail
that aren't expecting those extensions to be enabled. This patch
fixes various tests failing like that for an x86_64-linux-gnu
toolchain configured --with-arch=b
The attached patch fixes an issue with pointer subtraction (wrong type).
Committed as Rev. 208919.
Additionally I have merged the trunk into the branch, Rev. 208922.
Tobias
Index: gcc/fortran/ChangeLog.fortran-caf
===
--- gcc/fortr
> Hi,
>
> this patch fixes PR 60640 by creating thunks to clones when that is
> necessary to properly redirect edges to them. I mostly does what
> cgraph_add_thunk does and what analyze_function does to thunks. It
> fixes the testcases on trunk (it does not apply to 4.8, I have not
> looked how
Hi,
the inliner heuristic is organized as a greedy algorithm making inline
decisions in order defined by badness until inline limits are hit. The tricky
part is that the badness depends both on caller and callee (it is basically
size/time metric, that depends on callee, but caller provide context
Just a nit…
> 2014-03-28 Fabien Chêne
>
>* cp/init.c (perform_member_init): homogeneize uninitialized
>diagnostics.
Sentences begin with an upper case letter, and spelling… Homogenize..
On Mar 28, 2014, at 12:04 PM, Mike Stump wrote:
>
>> 2014-03-28 Vishnu K S
>>
>> * gcc/testsuite/gcc.dg/tree-ssa/isolate-1.c: Skip test for AVR
>> * gcc/testsuite/gcc.dg/tree-ssa/isolate-2.c: Ditto
>> * gcc/testsuite/gcc.dg/tree-ssa/isolate-3.c: Ditto
>> * gcc/testsuite/g
On Mar 28, 2014, at 6:23 AM, K_s, Vishnu wrote:
> Test pr59940.c is failing for AVR target because the test assumes the size
> of int as 32 bit and test expect to generate warnings for overflow and
> conversion while assigning 36-bit and 32 bit value respectively to variable
> si.
> Following pat
Hello!
> Here are more intrinsics that are missing. I know that gcc currently
> generates horrible code for most of them but I think it's more important
> to have the API in place, albeit non-optimal. Maybe this entices some
> one to add the necessary optimizations.
I agree that having non-opti
Hello,
I fixed an ICE in pr59599 due to a wrong number of arguments passed to
the ichar function, but I forgot to update the size of the buffer
containing the argument list. Fixed thusly.
I have tested the patch (attached) on x86_64-unknown-linux-gnu and
committed it as revision 208913.
Thanks to
Sweet. Yes please, in stage 1.
On Mar 28, 2014, at 3:16 AM, K_s, Vishnu wrote:
> The tests added in gcc.dg/tree-ssa/isolate-*.c is failing for AVR target,
> Because the isolate erroneous path pass needs -fdelete-null-pointer-checks
> option to be enabled. For AVR target that option is disabled, this cause
> the tests to fail.
On Fri, Mar 28, 2014 at 4:19 PM, Jakub Jelinek wrote:
> Before ix86_copy_addr_to_reg has been added, we've been using
> copy_addr_to_reg, which handles VOIDmode values just fine.
> But this new function just ICEs on those. As the function
> has been added for adding SUBREGs to TLS addresses, tho
In the mips--netbsdelf target gcc 4.9 lost the pre-definition of
__mips_o32, which is heavily used in NetBSD sources.
The obvious trivial patch adds it back.
Martin
--8-<--
Define __mips_o32 for -mabi=32
--- gcc/config/mips/netbsd.h.orig 2014-01-02 23:23:26.0 +0100
+++ gcc/config/
On 28/03/14 00:20, DJ Delorie wrote:
This is OK after 4.9 branches (i.e. stage1). I suspect we could add
AX to the first alternative, although I don't know if it will get
used. We could add HL to the second alternative to complete the
replacement of the 'r' constraint.
Yes, the missing AX in
> Actually after some additional invetstigation I decided to commit this
> patch. fixup_noreturn_call already cares about the return value but
> differently than the new Jakub's code.
Thanks for the quick fix, I confirm that the ACATS failures are all gone.
So we're left with the GIMPLE checking
On Fri, Mar 28, 2014 at 12:04:00PM -0600, Jeff Law wrote:
> Here's the updated patch. It uses simplify_gen_binary in expr.c to
> simplify the address expression as we're building it. It also uses
> copy_addr_to_reg in the x86 backend to avoid the possibility of
> generating non-canonical RTL ther
On 03/26/14 12:28, Jakub Jelinek wrote:
On Wed, Mar 26, 2014 at 12:17:43PM -0600, Jeff Law wrote:
On 03/26/14 12:12, Jakub Jelinek wrote:
On Wed, Mar 26, 2014 at 11:02:48AM -0600, Jeff Law wrote:
Bootstrapped and regression tested on x86_64-unknown-linux-gnu.
Verified it fixes the original and
On Fri, Mar 28, 2014 at 11:11:58AM +, pins...@gmail.com wrote:
> > On Mar 28, 2014, at 2:12 AM, James Greenhalgh
> > wrote:
> > Hi,
> >
> > There is no way to perform scalar addition in the vector register file,
> > but with the RTX costs in place we start rewriting (x << 1) to (x + x)
> > o
This patch replaces the temporary inline assembler for vtrn[q]_* in arm_neon.h
with equivalent calls to __builtin_shuffle. These are matched by existing
patterns in aarch64.c (aarch64_expand_vec_perm_const_1), outputting the same
assembler instructions. For two-element vectors, ZIP, UZP and TR
On Tue, Mar 25, 2014 at 3:52 PM, Kyrill Tkachov wrote:
> Hi all,
>
> In ARMv8-A there's a general expectation that AESE/AESMC and AESD/AESIMC
> sequences of the form:
>
> AESE Vn, _
> AESMC Vn, Vn
>
> will issue both instructions in a single cycle on super-scalar
> implementations. It would be nic
On Fri, Mar 28, 2014 at 6:30 AM, Richard Biener wrote:
>
> 2014-03-26 Richard Biener
>
> libiberty/
> * simple-object.c (simple_object_internal_read): Handle
> EINTR and short reads.
>
> lto-plugin/
> * lto-plugin.c (process_symtab): Use simple_object_int
On Fri, Mar 28, 2014 at 03:09:22PM +, pins...@gmail.com wrote:
>
>
> > On Mar 28, 2014, at 7:48 AM, James Greenhalgh
> > wrote:
> >
> > On Fri, Mar 28, 2014 at 11:11:58AM +, pins...@gmail.com wrote:
> >>> On Mar 28, 2014, at 2:12 AM, James Greenhalgh
> >>> wrote:
> >>> Hi,
> >>>
> >
On 03/28/2014 08:24 AM, Jakub Jelinek wrote:
> Here is the variant patch, which implements the above.
> Also bootstrapped/regtested on x86_64-linux and i686-linux.
>
> 2014-03-28 Jakub Jelinek
>
> PR c++/60689
> * c-tree.h (c_build_function_call_vec): New prototype.
> * c-typ
Hi!
Before ix86_copy_addr_to_reg has been added, we've been using
copy_addr_to_reg, which handles VOIDmode values just fine.
But this new function just ICEs on those. As the function
has been added for adding SUBREGs to TLS addresses, those will
never retunring CONST_INTs, so just using copy_addr
Jakub,
I did testing of this fix and bootstrap and regression testing were
OK, i.e. no new failures.
2014-03-28 14:49 GMT+04:00 Jakub Jelinek :
> On Fri, Mar 28, 2014 at 02:41:26PM +0400, Yuri Rumyantsev wrote:
>> Hi All,
>>
>> I found out that a field 'safelen" of struct loop is not copied in
>
On 03/28/2014 06:47 AM, Jakub Jelinek wrote:
* typeck.c (build_function_call_vec): Call resolve_overloaded_builtin.
I expect this will break in templates if arguments are dependent.
Jason
On Fri, Mar 28, 2014 at 01:46:09PM -0400, Jason Merrill wrote:
> On 03/28/2014 06:47 AM, Jakub Jelinek wrote:
> > * typeck.c (build_function_call_vec): Call resolve_overloaded_builtin.
>
> I expect this will break in templates if arguments are dependent.
The only problem with this patch is po
On Wed, Mar 19, 2014 at 9:55 AM, Kyrill Tkachov wrote:
> Hi all,
>
> This patch adds a recogniser for the bitmask,shift,orr sequence of
> instructions that can be used to reverse the bytes in 16-bit halfwords (for
> the sequence itself look at the testcase included in the patch). This can be
> imp
On 28/03/14 14:21, Ramana Radhakrishnan wrote:
On Wed, Mar 19, 2014 at 9:55 AM, Kyrill Tkachov wrote:
Hi all,
This patch adds a recogniser for the bitmask,shift,orr sequence of
instructions that can be used to reverse the bytes in 16-bit halfwords (for
the sequence itself look at the testcase
On Wed, Mar 19, 2014 at 9:56 AM, Kyrill Tkachov wrote:
> Hi all,
>
> This is the arm equivalent of patch [2/3] in the series that adds combine
> patterns for the bitwise operations leading to a rev16 instruction.
> It reuses the functions that were put in aarch-common.c to properly cost
> these op
On Wed, Mar 19, 2014 at 9:55 AM, Kyrill Tkachov wrote:
> Hi all,
>
> In order to properly cost the rev16 instruction we need a new field in the
> cost tables.
> This patch adds that and specifies its value for the existing cost tables.
> Since rev16 is used to implement the BSWAP operation we add
Test pr59940.c is failing for AVR target because the test assumes the size
of int as 32 bit and test expect to generate warnings for overflow and
conversion while assigning 36-bit and 32 bit value respectively to variable si.
Following patch define a 32 bit type with SI mode and use it.
2014-03-28
> On Mar 28, 2014, at 7:48 AM, James Greenhalgh
> wrote:
>
> On Fri, Mar 28, 2014 at 11:11:58AM +, pins...@gmail.com wrote:
>>> On Mar 28, 2014, at 2:12 AM, James Greenhalgh
>>> wrote:
>>> Hi,
>>>
>>> There is no way to perform scalar addition in the vector register file,
>>> but with t
On Fri, 28 Mar 2014, Marek Polacek wrote:
> PR51088 contains some Really Bizzare code. We should tell users
> not to do any shenanigans like that.
>
> Ok for trunk?
I don't think a doc patch resolves this bug. The compiler should never
generate code with an undefined reference to a local labe
This adds DejaGNU tests of the existing AArch64 vuzp_* intrinsics, both checking
the assembler output and the runtime results. Test bodies are in separate files
ready to reuse for ARM in the third patch.
Putting these in a new subdirectory with the ZIP Intrinsics tests, using
simd.exp added ther
> > > Bootstrapped/regtested x86_64-linux, comitted.
> >
> > Not with Ada apparently, resulting in
> >
> > === acats tests ===
> > FAIL: c34007d
> > FAIL: c34007g
> > FAIL: c34007s
> > FAIL: c37213j
> > FAIL: c37213k
> > FAIL: c37213l
> > FAIL: ce2201g
> > FAIL: c
On Fri, Mar 28, 2014 at 11:47:52AM +0100, Jakub Jelinek wrote:
> Yet another possibility would be to rename all calls in C FE to
> build_function_call_vec to say c_build_function_call_vec and add that
> function which would call resolve_overloaded_builtin and then tail call to
> build_function_call
Final patch in series, adds new tests of the ARM TRN Intrinsics, that also check
the execution results, reusing the test bodies introduced into AArch64 in the
first patch. (These tests subsume the autogenerated ones in
testsuite/gcc.target/arm/neon/ that only check assembler output.)
Tests use gc
Hi,
after much confusion on my part, this is the proper fix for PR 60647.
IPA-SRA can get confused a lot when a formal parameter is a pointer
but the corresponding actual argument is not. So this patch adds a
check that their types pass useless_type_conversion_p check.
Bootstrapped and tested on
UBSan detected that we were trying to set a non-existent bit in a mask.
I don't think it has mattered before now because when this happens the
value in the mask is not used. However, better safe than sorry.
Andrew.
2014-03-28 Andrew Haley
* boehm.c (mark_reference_fields): Avoid un
On Fri, Mar 28, 2014 at 5:18 PM, Kyrill Tkachov wrote:
> On 28/03/14 14:18, Ramana Radhakrishnan wrote:
>>
>> On Tue, Mar 25, 2014 at 3:51 PM, Kyrill Tkachov
>> wrote:
>>>
>>> Hi all,
>>>
>>> This two-patch series adds scheduling information for the ARMv8-A Crypto
>>> instructions on the Cortex-A
On 28/03/14 17:18, Kyrill Tkachov wrote:
On 28/03/14 14:18, Ramana Radhakrishnan wrote:
On Tue, Mar 25, 2014 at 3:51 PM, Kyrill Tkachov wrote:
Hi all,
This two-patch series adds scheduling information for the ARMv8-A Crypto
instructions on the Cortex-A53.
This first patch does some preliminar
Hi,
this patch fixes PR 60640 by creating thunks to clones when that is
necessary to properly redirect edges to them. I mostly does what
cgraph_add_thunk does and what analyze_function does to thunks. It
fixes the testcases on trunk (it does not apply to 4.8, I have not
looked how easily fixable
On 28 March 2014 14:52, Ramana Radhakrishnan wrote:
> To my mind on ARM / AArch64 this actually helps anyone using the
> crypto intrinsics on A53 hardware today and it would be good to get
> this into 4.9. Again I perceive this as low risk on ARM (AArch32) as
> this is not a default tuning optio
On Fri, Mar 28, 2014 at 05:35:12PM +0100, Martin Jambor wrote:
> after much confusion on my part, this is the proper fix for PR 60647.
> IPA-SRA can get confused a lot when a formal parameter is a pointer
> but the corresponding actual argument is not. So this patch adds a
> check that their types
On Fri, Mar 28, 2014 at 04:52:39PM +, Marcus Shawcroft wrote:
> On 28 March 2014 14:52, Ramana Radhakrishnan
> wrote:
>
> > To my mind on ARM / AArch64 this actually helps anyone using the
> > crypto intrinsics on A53 hardware today and it would be good to get
> > this into 4.9. Again I perc
On 28/03/14 14:18, Ramana Radhakrishnan wrote:
On Tue, Mar 25, 2014 at 3:51 PM, Kyrill Tkachov wrote:
Hi all,
This two-patch series adds scheduling information for the ARMv8-A Crypto
instructions on the Cortex-A53.
This first patch does some preliminary restructuring to allow the arm and
aarch
On 19 March 2014 09:56, Kyrill Tkachov wrote:
> Hi all,
>
> This patch depends on the series started at
> http://gcc.gnu.org/ml/gcc-patches/2014-03/msg00933.html but is not really a
> part of it. It just adds costing of the bswap operation using the new rev
> field in the rtx cost tables since we
OK.
Jason
On 19 March 2014 09:55, Kyrill Tkachov wrote:
> [gcc/]
> 2014-03-19 Kyrylo Tkachov
>
> * config/aarch64/aarch64.md (rev162): New pattern.
> (rev162_alt): Likewise.
> * config/aarch64/aarch64.c (aarch64_rtx_costs): Handle rev16 case.
> * config/arm/aarch-common.c (aarch_rev16_sh
On 03/27/2014 05:32 PM, Fabien Chêne wrote:
+ permerror (DECL_SOURCE_LOCATION (current_function_decl),
+"uninitialized reference member in %q#T", type);
+ inform (DECL_SOURCE_LOCATION (member),
+ "%q#D should be initialized", mem
On 03/28/2014 06:31 AM, Jakub Jelinek wrote:
Ok for trunk?
Yes, thanks.
Jason
on 19/03/2014 12:03 Andriy Gapon said the following:
>
> I observe the following minor annoyance on FreeBSD systems where cpp is GCC's
> cpp. If a DTrace script has the following shebang line:
> #!/usr/sbin/dtrace -Cs
> then the following warning is produced when the script is run:
> cc1: warning
On Fri, Mar 28, 2014 at 2:05 PM, Martin Liška wrote:
> Hi,
>I would like to add corresponding ipa.exp file for g++ that let me run:
> make -k check RUNTESTFLAGS="ipa.exp"
You can use
RUNTESTFLAGS="dg.exp=ipa/*.C"
Richard.
> Changelog:
>
> 2014-03-28 Martin Liska
>
> * g++.dg/ipa.epx
On Fri, 28 Mar 2014, Ramana Radhakrishnan wrote:
> On Tue, Mar 25, 2014 at 3:52 PM, Kyrill Tkachov
> wrote:
> > Hi all,
> >
> > In ARMv8-A there's a general expectation that AESE/AESMC and AESD/AESIMC
> > sequences of the form:
> >
> > AESE Vn, _
> > AESMC Vn, Vn
> >
> > will issue both instruct
The following patch fixes
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60675
LRA assigned hard reg 30 to TImode subreg of DImode pseudo but it was
wrong as hard reg 31 is unavailable for the allocation.
The patch was bootstrapped and tested on x86-64 and aarch64.
Committed as rev. 208900.
20
Much like the ZIP and UZP intrinsics, the vtrn[q]_* intrinsics are implemented
with inline __asm__, which blocks compiler analysis. This series replaces those
calls with __builtin_shuffle, which produce the same** assembler instructions.
** except for two-element vectors, where UZP, ZIP and TRN
On Tue, Mar 25, 2014 at 3:51 PM, Kyrill Tkachov wrote:
> Hi all,
>
> This two-patch series adds scheduling information for the ARMv8-A Crypto
> instructions on the Cortex-A53.
> This first patch does some preliminary restructuring to allow the arm and
> aarch64 backends to share the is_neon_type a
Jakub Jelinek writes:
> Seems it fails on all ilp32 targets I've tried and succeeds on all lp64
> targets (including ia64), so I think we should do following.
> Ok for trunk?
Looks right to me, but I'd like to defer to Jason as the subject-matter
expert.
Thanks.
Rainer
--
PR51088 contains some Really Bizzare code. We should tell users
not to do any shenanigans like that.
Ok for trunk?
2014-03-28 Marek Polacek
PR c/51088
* doc/extend.texi (Statement Exprs): Add note about taking
addresses of labels inside of statement expressions.
diff
Hi,
This affects only arm-none-eabi targets and those using t-aprofile in
their multilib lists. The problem here is that when the A12 support was
added, we mistakenly added this to the MULTILIB_MATCHES rule for the A15
rather than putting out a separate line for this.
Fixed thusly and veri
On Wed, 26 Mar 2014, Richard Biener wrote:
> On March 26, 2014 4:51:58 PM CET, Ian Lance Taylor wrote:
> >On Wed, Mar 26, 2014 at 8:38 AM, Richard Biener
> >wrote:
> >>
> >> - got = read (descriptor, buffer, size);
> >> - if (got < 0)
> >> + do
> >> {
> >> - *errmsg = "read";
> >> -
Hi Martin,
> Hi,
>I would like to add corresponding ipa.exp file for g++ that let me run:
> make -k check RUNTESTFLAGS="ipa.exp"
>
> Changelog:
>
> 2014-03-28 Martin Liska
>
> * g++.dg/ipa.epx: Anologous file added to g++.dg folder.
Two typos. Besides, this should be
* g++.dg
Hi,
I would like to add corresponding ipa.exp file for g++ that let me
run: make -k check RUNTESTFLAGS="ipa.exp"
Changelog:
2014-03-28 Martin Liska
* g++.dg/ipa.epx: Anologous file added to g++.dg folder.
OK for trunk?
Thank you,
Martin
diff --git a/gcc/testsuite/g++.dg/ipa/ipa.ex
Hi,
S/390 does not not define LOGICAL_OP_NON_SHORT_CIRCUIT but its default
value depends on the branch cost. On S/390 we set a branch cost of 1
which makes us a logical_op_short_circuit target.
This "fixes" the following testcases:
< FAIL: gcc.dg/binop-xor1.c scan-tree-dump-times optimized "\\\
Dear Tobias,
This is, of course, fine since it is 'obvious' (in my opinion at least).
Thanks for the patch
Paul
On 27 March 2014 21:05, Tobias Burnus wrote:
> An early * PING* for this wrong-code issue.
>
>
> Tobias Burnus wrote:
>>
>> This patch fixes part of the problems of the PR. The probl
> On Mar 28, 2014, at 2:12 AM, James Greenhalgh
> wrote:
>
>
> Hi,
>
> There is no way to perform scalar addition in the vector register file,
> but with the RTX costs in place we start rewriting (x << 1) to (x + x)
> on almost all cores. The code which makes this decision has no idea that w
On Fri, Mar 28, 2014 at 02:41:26PM +0400, Yuri Rumyantsev wrote:
> Hi All,
>
> I found out that a field 'safelen" of struct loop is not copied in copy_loops.
>
> Is it OK for trunk?
Ok if it passes bootstrap/regtest.
> 2014-03-28 Yuri Rumyantsev
>
> * tree-inline.c (copy_loops): Add missed
Hi!
__atomic_exchange doesn't work in C++. The problem is that
add_atomic_size_parameter, if there is no room in params vector, creates
new params vector big enough that the extra argument fixs in, but doesn't
add the extra argument in, because it relies on the subsequent
build_function_call_vec
Hi All,
I found out that a field 'safelen" of struct loop is not copied in copy_loops.
Is it OK for trunk?
ChangeLog:
2014-03-28 Yuri Rumyantsev
* tree-inline.c (copy_loops): Add missed copy of 'safelen'.
copy-loops-fix
Description: Binary data
On Fri, Mar 28, 2014 at 10:06:45AM +0100, Rainer Orth wrote:
> > FAIL: g++.dg/abi/thunk6.C -std=c++11 scan-assembler _ZTv0_n32_N1CD1Ev
> >
> > $ grep _ZTv0_ thunk6.s
> > .globl _ZTv0_n16_N1CD1Ev
> > .type _ZTv0_n16_N1CD1Ev, @function
> > _ZTv0_n16_N1CD1Ev:
> > .size _Z
On Thu, Mar 27, 2014 at 12:02:01PM +0100, Andreas Schwab wrote:
> > --- testsuite/g++.dg/torture/pr60315.C (revision 0)
> > +++ testsuite/g++.dg/torture/pr60315.C (revision 0)
> > @@ -0,0 +1,32 @@
> > +// { dg-do compile }
> > +struct Base {
> > +virtual int f() = 0;
> > +};
> > +
> >
> However, the first call is for blocks with incoming abnormal edges.
> If these are empty, the change as I wrote it yesterday is fine, but not
> when they are non-empty; in that case, we should indeed insert before the
> first instruction in that block.
OK, so the issue is specific to empty basic
Hi all,
The tests added in gcc.dg/tree-ssa/isolate-*.c is failing for AVR target,
Because the isolate erroneous path pass needs -fdelete-null-pointer-checks
option to be enabled. For AVR target that option is disabled, this cause
the tests to fail. Following Patch skip the isolate-* tests if
"ke
PR c++/60573
* name-lookup.h (cp_binding_level): New transient field defining_class_p
to indicate whether a scope is in the process of defining a class.
* semantics.c (begin_class_definition): Set defining_class_p.
* name-lookup.c (leave_scope): Reset definin
On 2014-03-27 21:16, Adam Butcher wrote:
On 2014-03-27 20:45, Adam Butcher wrote:
PR c++/60573
* name-lookup.h (cp_binding_level): New field scope_defines_class_p.
* semantics.c (begin_class_definition): Set scope_defines_class_p.
* pt.c (instantiate_class_template_1): Likewise.
* parser.c (synt
Ping!
On 03/23/2014 03:20 AM, Dimitris Papavasiliou wrote:
Ping!
On 03/13/2014 11:54 AM, Dimitris Papavasiliou wrote:
Ping!
On 03/06/2014 07:44 PM, Dimitris Papavasiliou wrote:
Ping!
On 02/27/2014 11:44 AM, Dimitris Papavasiliou wrote:
Ping!
On 02/20/2014 12:11 PM, Dimitris Papavasiliou w
Hi,
There is no way to perform scalar addition in the vector register file,
but with the RTX costs in place we start rewriting (x << 1) to (x + x)
on almost all cores. The code which makes this decision has no idea that we
will end up doing this (it happens well before reload) and so we end up wi
Andreas Schwab writes:
> Jason Merrill writes:
>
>> diff --git a/gcc/testsuite/g++.dg/abi/thunk6.C
>> b/gcc/testsuite/g++.dg/abi/thunk6.C
>> new file mode 100644
>> index 000..e3d07f2
>> --- /dev/null
>> +++ b/gcc/testsuite/g++.dg/abi/thunk6.C
>> @@ -0,0 +1,18 @@
>> +// PR c++/60566
>> +// W
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Terry Guo
> Sent: Friday, March 28, 2014 3:48 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [Patch]Simplify SUBREG with operand whose target bits are cleared
> by AND operation
Hi there,
When compile below case for ARM Thumb-2 target:
long long int
test (unsigned long long int a, unsigned int b)
{
return (a & 0x) * b;
}
I find the GCC function simplify_subreg fails to simplify rtx (subreg:SI
(and:DI (reg/v:DI 115 [ a ]) (const_int 4294967295 [0x])) 4)
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