[gcc r15-4566] Fix ICE due to isa mismatch for the builtins.

https://gcc.gnu.org/g:403e361d5aa620e77c9832578b2409a0fdd79d96 commit r15-4566-g403e361d5aa620e77c9832578b2409a0fdd79d96 Author: liuhongt Date: Tue Oct 22 01:54:40 2024 -0700 Fix ICE due to isa mismatch for the builtins. gcc/ChangeLog: PR target/117240

[gcc r14-10852] Fix ICE due to subreg:us_truncate.

https://gcc.gnu.org/g:71a0cf699b6a2dc03abec53aeafab8b70db2bb07 commit r14-10852-g71a0cf699b6a2dc03abec53aeafab8b70db2bb07 Author: liuhongt Date: Tue Oct 29 02:09:39 2024 -0700 Fix ICE due to subreg:us_truncate. Force_operand issues an ICE when input is (subreg:DI (us_truncate:

[gcc r15-4775] Fix ICE due to subreg:us_truncate.

https://gcc.gnu.org/g:bc0eeccf27a084461a2d5661e23468350acb43da commit r15-4775-gbc0eeccf27a084461a2d5661e23468350acb43da Author: liuhongt Date: Tue Oct 29 02:09:39 2024 -0700 Fix ICE due to subreg:us_truncate. Force_operand issues an ICE when input is (subreg:DI (us_truncate:V

[gcc r15-4954] Support vector float_truncate for SF to BF.

https://gcc.gnu.org/g:a17acf4f25f0ce9b8dce24f25867500a3b093b57 commit r15-4954-ga17acf4f25f0ce9b8dce24f25867500a3b093b57 Author: liuhongt Date: Wed Oct 23 00:51:00 2024 -0700 Support vector float_truncate for SF to BF. Generate native instruction whenever possible, otherwise use v

[gcc r15-4955] Support vector float_extend from __bf16 to float.

https://gcc.gnu.org/g:648bd1fcc6acfc56e08f4ad8146a80910cfacfd7 commit r15-4955-g648bd1fcc6acfc56e08f4ad8146a80910cfacfd7 Author: liuhongt Date: Wed Oct 23 23:51:20 2024 -0700 Support vector float_extend from __bf16 to float. It's supported by vector permutation with zero vector.

[gcc r12-10793] Fix ICE due to subreg:us_truncate.

https://gcc.gnu.org/g:d0a932fb53ccdf5155db90632901c55446b8 commit r12-10793-gd0a932fb53ccdf5155db90632901c55446b8 Author: liuhongt Date: Tue Oct 29 02:09:39 2024 -0700 Fix ICE due to subreg:us_truncate. Force_operand issues an ICE when input is (subreg:DI (us_truncate:

[gcc r13-9157] Fix ICE due to subreg:us_truncate.

https://gcc.gnu.org/g:28ea5a4ec3e9e49439fdb912ef4edeebfdae881d commit r13-9157-g28ea5a4ec3e9e49439fdb912ef4edeebfdae881d Author: liuhongt Date: Tue Oct 29 02:09:39 2024 -0700 Fix ICE due to subreg:us_truncate. Force_operand issues an ICE when input is (subreg:DI (us_truncate:V

[gcc r15-5071] Guard truncate from vector float to vector __bf16 with !flag_rounding_math && HONOR_NANS (BFmode).

https://gcc.gnu.org/g:de867e8da30bf5e0cb51c3946ec43c3c4778d4a0 commit r15-5071-gde867e8da30bf5e0cb51c3946ec43c3c4778d4a0 Author: liuhongt Date: Wed Nov 6 18:15:42 2024 -0800 Guard truncate from vector float to vector __bf16 with !flag_rounding_math && HONOR_NANS (BFmode). hw inst

[gcc r12-10784] Fix ICE due to isa mismatch for the builtins.

https://gcc.gnu.org/g:ab84a8a4b78990942e006e9f060dc2705f2c6d8f commit r12-10784-gab84a8a4b78990942e006e9f060dc2705f2c6d8f Author: liuhongt Date: Tue Oct 22 01:54:40 2024 -0700 Fix ICE due to isa mismatch for the builtins. gcc/ChangeLog: PR target/117240

[gcc r15-3885] Define VECTOR_STORE_FLAG_VALUE

https://gcc.gnu.org/g:78eef8919e2f2973ed7750ba66f5726e70614d07 commit r15-3885-g78eef8919e2f2973ed7750ba66f5726e70614d07 Author: liuhongt Date: Mon Sep 23 11:06:04 2024 +0800 Define VECTOR_STORE_FLAG_VALUE gcc/ChangeLog: * config/i386/i386.h (VECTOR_STORE_FLAG_VAL

[gcc r15-4371] Adjust testcase to avoid scan FIX in REG_EQUIV.

https://gcc.gnu.org/g:a8b4ea1bcc10b5253992f4b932aec6862aef32fa commit r15-4371-ga8b4ea1bcc10b5253992f4b932aec6862aef32fa Author: liuhongt Date: Tue Oct 15 11:17:20 2024 +0800 Adjust testcase to avoid scan FIX in REG_EQUIV. Also add hard_float target to avoid failed on arm-eabi.

[gcc r15-4400] Don't lower vpcmpu to pcmpgt since the latter is for signed comparison.

https://gcc.gnu.org/g:21e2cd65add9070292313f8e12e8731d0aa2c869 commit r15-4400-g21e2cd65add9070292313f8e12e8731d0aa2c869 Author: liuhongt Date: Tue Oct 8 16:18:31 2024 +0800 Don't lower vpcmpu to pcmpgt since the latter is for signed comparison. r15-1737-gb06a108f0fbffe lower AVX5

[gcc r15-4399] Canonicalize (vec_merge (fma: op2 op1 op3) (match_dup 1)) mask) to (vec_merge (fma: op1 op2 op3) (ma

https://gcc.gnu.org/g:edf4db8355dead3413bad64f6a89bae82dabd0ad commit r15-4399-gedf4db8355dead3413bad64f6a89bae82dabd0ad Author: liuhongt Date: Mon Oct 14 13:09:59 2024 +0800 Canonicalize (vec_merge (fma: op2 op1 op3) (match_dup 1)) mask) to (vec_merge (fma: op1 op2 op3) (match_dup 1)) ma

[gcc r15-4398] Canonicalize (vec_merge (fma op2 op1 op3) op1 mask) to (vec_merge (fma op1 op2 op3) op1 mask).

https://gcc.gnu.org/g:330782a1b6cfe881ad884617ffab441aeb1c2b5c commit r15-4398-g330782a1b6cfe881ad884617ffab441aeb1c2b5c Author: liuhongt Date: Mon Oct 14 17:16:13 2024 +0800 Canonicalize (vec_merge (fma op2 op1 op3) op1 mask) to (vec_merge (fma op1 op2 op3) op1 mask). For x86 ma

[gcc r15-5639] Fix uninitialized operands[2] in vec_unpacks_hi_v4sf.

https://gcc.gnu.org/g:ba4cf2e296d8d5950c3d356fa6b6efcad00d0189 commit r15-5639-gba4cf2e296d8d5950c3d356fa6b6efcad00d0189 Author: liuhongt Date: Thu Nov 21 23:57:38 2024 -0800 Fix uninitialized operands[2] in vec_unpacks_hi_v4sf. It could cause weired spill in RA when register pres

[gcc r14-10979] Fix uninitialized operands[2] in vec_unpacks_hi_v4sf.

https://gcc.gnu.org/g:4a63cc6de77481878ec31e1e6ac30e22c50b063a commit r14-10979-g4a63cc6de77481878ec31e1e6ac30e22c50b063a Author: liuhongt Date: Thu Nov 21 23:57:38 2024 -0800 Fix uninitialized operands[2] in vec_unpacks_hi_v4sf. It could cause weired spill in RA when register pre

[gcc r15-5489] Add microarchtecture tunable for pass_align_tight_loops [PR117438]

https://gcc.gnu.org/g:6350e956d1a74963a62bedabef3d4a1a3f2d4852 commit r15-5489-g6350e956d1a74963a62bedabef3d4a1a3f2d4852 Author: MayShao-oc Date: Thu Nov 7 10:57:02 2024 +0800 Add microarchtecture tunable for pass_align_tight_loops [PR117438] Hi Hongtao: Add m_CASCADELAK, a

[gcc r13-9216] Fix uninitialized operands[2] in vec_unpacks_hi_v4sf.

https://gcc.gnu.org/g:0eb8c19cb45fc004b7039fa22ff9021604d80dbc commit r13-9216-g0eb8c19cb45fc004b7039fa22ff9021604d80dbc Author: liuhongt Date: Thu Nov 21 23:57:38 2024 -0800 Fix uninitialized operands[2] in vec_unpacks_hi_v4sf. It could cause weired spill in RA when register pres

[gcc r12-10832] Fix uninitialized operands[2] in vec_unpacks_hi_v4sf.

https://gcc.gnu.org/g:89a27cf6b1354cc80d834d71f7a3aa137d605e94 commit r12-10832-g89a27cf6b1354cc80d834d71f7a3aa137d605e94 Author: liuhongt Date: Thu Nov 21 23:57:38 2024 -0800 Fix uninitialized operands[2] in vec_unpacks_hi_v4sf. It could cause weired spill in RA when register pre

[gcc r15-6097] Fix inaccuracy in cunroll/cunrolli when considering what's innermost loop.

https://gcc.gnu.org/g:ee2f19b0937b5efc0b23c4319cbd4a38b27eac6e commit r15-6097-gee2f19b0937b5efc0b23c4319cbd4a38b27eac6e Author: liuhongt Date: Mon Dec 2 01:54:59 2024 -0800 Fix inaccuracy in cunroll/cunrolli when considering what's innermost loop. r15-919-gef27b91b62c3aa removed

[gcc r15-6844] Refactor ix86_expand_vecop_qihi2.

https://gcc.gnu.org/g:0e05b793fba2a9bea9f0fbb1f068679f5dadf514 commit r15-6844-g0e05b793fba2a9bea9f0fbb1f068679f5dadf514 Author: liuhongt Date: Wed Jan 8 23:11:17 2025 -0800 Refactor ix86_expand_vecop_qihi2. Since there's regression to use vpermq, and it's manually disabled by

[gcc r15-6940] Fix typo to avoid ICE.

https://gcc.gnu.org/g:3872daa5767622d1f8b086050996c85604db7514 commit r15-6940-g3872daa5767622d1f8b086050996c85604db7514 Author: liuhongt Date: Wed Jan 15 19:09:24 2025 -0800 Fix typo to avoid ICE. gcc/ChangeLog: PR target/118489 * config/i386/sse.md (

[gcc r15-8283] Mark gcc.target/i386/apx-ndd-tls-1b.c as xfail.

https://gcc.gnu.org/g:be671ec1f30ecd55aaff09048afb2a619018cb8a commit r15-8283-gbe671ec1f30ecd55aaff09048afb2a619018cb8a Author: liuhongt Date: Sun Mar 16 22:28:44 2025 -0700 Mark gcc.target/i386/apx-ndd-tls-1b.c as xfail. It looks like the testcase is fragile, it's supposed to ch

[gcc r15-8461] Use ix86_fp_comparison_operator in cbranchbf4 to avoid ICE.

https://gcc.gnu.org/g:62a6cafd7f55c6e88a9780b91039257572038535 commit r15-8461-g62a6cafd7f55c6e88a9780b91039257572038535 Author: liuhongt Date: Mon Mar 17 22:47:11 2025 -0700 Use ix86_fp_comparison_operator in cbranchbf4 to avoid ICE. *jcc only supports ix86_fp_comparison_operator

[gcc r15-9473] Revert documents from r11-344-g0fec3f62b9bfc0

https://gcc.gnu.org/g:fa58ff249a0e63a721ccb6d770c86523d84a212a commit r15-9473-gfa58ff249a0e63a721ccb6d770c86523d84a212a Author: liuhongt Date: Sun Apr 13 19:40:51 2025 -0700 Revert documents from r11-344-g0fec3f62b9bfc0 gcc/ChangeLog: PR target/108134

[gcc r16-46] Generate 2 FMA instructions in ix86_expand_swdivsf.

https://gcc.gnu.org/g:e1098c7b08d9e6018f60dae7a14c5ad621618223 commit r16-46-ge1098c7b08d9e6018f60dae7a14c5ad621618223 Author: hongtao.liu Date: Thu Apr 17 09:07:55 2025 +0200 Generate 2 FMA instructions in ix86_expand_swdivsf. When FMA is available, N-R step can be rewritten with

[gcc r16-91] Accept allones or 0 operand for vcond_mask op1.

https://gcc.gnu.org/g:f72a2d221539cede358f2487b94bc370c6fc44b5 commit r16-91-gf72a2d221539cede358f2487b94bc370c6fc44b5 Author: liuhongt Date: Sun Mar 30 20:15:41 2025 -0700 Accept allones or 0 operand for vcond_mask op1. Since ix86_expand_sse_movcc will simplify them into a simple

[gcc r16-105] target: [PR103750] Also handle avx512 kmask & immediate 15 or 3 when VF is 4/2.

https://gcc.gnu.org/g:599bca27dc37b3f7979bd6af30a357104f2b90c1 commit r16-105-g599bca27dc37b3f7979bd6af30a357104f2b90c1 Author: liuhongt Date: Mon Apr 7 23:50:53 2025 -0700 target: [PR103750] Also handle avx512 kmask & immediate 15 or 3 when VF is 4/2. Since the upper bits are al

[gcc r16-269] Remove other processors from X86_TUNE_DEST_FALSE_DEP_FOR_GLC except GLC

https://gcc.gnu.org/g:1ad6e171b126a82f38b1e8cbfd207f1d91c58a59 commit r16-269-g1ad6e171b126a82f38b1e8cbfd207f1d91c58a59 Author: liuhongt Date: Mon Apr 28 07:45:50 2025 -0700 Remove other processors from X86_TUNE_DEST_FALSE_DEP_FOR_GLC except GLC Since the tune if only for GLC(sapp

[gcc r14-11698] Remove other processors from X86_TUNE_DEST_FALSE_DEP_FOR_GLC except GLC

https://gcc.gnu.org/g:96729baa9ef0e9f571e219c7289dbec64768c7c8 commit r14-11698-g96729baa9ef0e9f571e219c7289dbec64768c7c8 Author: liuhongt Date: Mon Apr 28 07:45:50 2025 -0700 Remove other processors from X86_TUNE_DEST_FALSE_DEP_FOR_GLC except GLC Since the tune if only for GLC(sa

[gcc r15-9597] Remove other processors from X86_TUNE_DEST_FALSE_DEP_FOR_GLC except GLC

https://gcc.gnu.org/g:972a03737284b8611ec4e6315f6ca04d56ec05bf commit r15-9597-g972a03737284b8611ec4e6315f6ca04d56ec05bf Author: liuhongt Date: Mon Apr 28 07:45:50 2025 -0700 Remove other processors from X86_TUNE_DEST_FALSE_DEP_FOR_GLC except GLC Since the tune if only for GLC(sap

[gcc r13-9621] Remove other processors from X86_TUNE_DEST_FALSE_DEP_FOR_GLC except GLC

https://gcc.gnu.org/g:96040fda2f324156d8e39f42dd6df35e0dc0661b commit r13-9621-g96040fda2f324156d8e39f42dd6df35e0dc0661b Author: liuhongt Date: Mon Apr 28 07:45:50 2025 -0700 Remove other processors from X86_TUNE_DEST_FALSE_DEP_FOR_GLC except GLC Since the tune if only for GLC(sap

[gcc r16-274] Annotate empty bb with all debug_stmt with location of phi in the single_succ.

https://gcc.gnu.org/g:59e853308bd797f91df15fd0fa65a3b5ce2cf4a2 commit r16-274-g59e853308bd797f91df15fd0fa65a3b5ce2cf4a2 Author: hongtao.liu Date: Wed Jan 22 07:44:01 2025 +0100 Annotate empty bb with all debug_stmt with location of phi in the single_succ. For an empty BB with all

[gcc r16-164] Refactor msse4 and mno-sse4.

https://gcc.gnu.org/g:d85444a3b00c9a6fce56459af5ec081439a9aaa0 commit r16-164-gd85444a3b00c9a6fce56459af5ec081439a9aaa0 Author: liuhongt Date: Tue Apr 1 00:30:07 2025 -0700 Refactor msse4 and mno-sse4. gcc/ChangeLog: PR target/119549 * common/config/i3

[gcc r16-435] Fix name mismatch for fortran.

https://gcc.gnu.org/g:ae987baeb5fb70877fd007db80b77e374f676c76 commit r16-435-gae987baeb5fb70877fd007db80b77e374f676c76 Author: hongtao.liu Date: Tue Jan 14 01:13:22 2025 +0100 Fix name mismatch for fortran. Function name in afdo_string_table is step3d_t_tile. but DECL_ASSEMBL

[gcc r16-605] Extend vect_recog_cond_expr_convert_pattern to handle floating point type.

https://gcc.gnu.org/g:e3385fed3fc61ac505fb5c1ffa09758a6f2489eb commit r16-605-ge3385fed3fc61ac505fb5c1ffa09758a6f2489eb Author: liuhongt Date: Mon Apr 7 20:12:00 2025 -0700 Extend vect_recog_cond_expr_convert_pattern to handle floating point type. For floating point, !flag_trappin

[gcc r16-619] Consider frequency in cost estimation when converting scalar to vector.

https://gcc.gnu.org/g:f0d36c822c8b0918583c6bc3b1db01f2bb7f226b commit r16-619-gf0d36c822c8b0918583c6bc3b1db01f2bb7f226b Author: liuhongt Date: Tue Dec 17 22:32:31 2024 -0800 Consider frequency in cost estimation when converting scalar to vector. n some benchmark, I notice stv fail

[gcc r16-767] Add pattern match in match.pd for .AVG_CEIL

https://gcc.gnu.org/g:72f0b446d2c03866ebe4cae125e32fef598e924d commit r16-767-g72f0b446d2c03866ebe4cae125e32fef598e924d Author: liuhongt Date: Tue Feb 25 22:48:27 2025 -0800 Add pattern match in match.pd for .AVG_CEIL 1) Optimize (a >> 1) + (b >> 1) + ((a | b) & 1) to .AVG_CEIL (a

[gcc r16-750] Extend vect_recog_cond_expr_convert_pattern to handle REAL_CST

https://gcc.gnu.org/g:1e579e2eb5bf69419222a10afc854565b6bc0d78 commit r16-750-g1e579e2eb5bf69419222a10afc854565b6bc0d78 Author: liuhongt Date: Sun May 11 23:21:30 2025 -0700 Extend vect_recog_cond_expr_convert_pattern to handle REAL_CST REAL_CST is handled if it can be represented

[gcc r16-924] For datarefs with big gap, split them into different groups.

https://gcc.gnu.org/g:1bc5b47f5b06dc4e8d2e7b622a7100b40b8e6b27 commit r16-924-g1bc5b47f5b06dc4e8d2e7b622a7100b40b8e6b27 Author: liuhongt Date: Tue Mar 11 18:40:07 2025 -0700 For datarefs with big gap, split them into different groups. The patch tries to solve miss vectorization fo

[gcc r16-643] Update libbid according to the latest Intel Decimal Floating-Point Math Library.

https://gcc.gnu.org/g:38163c874a3211ea4b4c48d13e4e27a56d78ebe7 commit r16-643-g38163c874a3211ea4b4c48d13e4e27a56d78ebe7 Author: liuhongt Date: Mon May 12 18:26:13 2025 -0700 Update libbid according to the latest Intel Decimal Floating-Point Math Library. The Intel Decimal Floatin

[gcc r16-1298] Also handle avx512 kmask & immediate 15 or 3 when VF is 4/2.

https://gcc.gnu.org/g:cdfa5fe03512f7ac5a293480f634df68fc973060 commit r16-1298-gcdfa5fe03512f7ac5a293480f634df68fc973060 Author: liuhongt Date: Tue Jun 3 14:12:23 2025 +0800 Also handle avx512 kmask & immediate 15 or 3 when VF is 4/2. like r16-105-g599bca27dc37b3, the patch handle

[gcc r16-1647] Don't duplicate setup code cost when do group-candidate cost calucalution.

https://gcc.gnu.org/g:c06979ff95748559da0c2d3aa4eda9d5999eaaf6 commit r16-1647-gc06979ff95748559da0c2d3aa4eda9d5999eaaf6 Author: hongtao.liu Date: Wed Mar 5 12:25:32 2025 +0100 Don't duplicate setup code cost when do group-candidate cost calucalution. - /* Uses in a group can sha

[gcc r16-2623] Eliminate redundant vpextrq/vpinsrq when move TI to V4SI.

https://gcc.gnu.org/g:6a466839340dce3b596b3ae5ce85bd05a067ae00 commit r16-2623-g6a466839340dce3b596b3ae5ce85bd05a067ae00 Author: liuhongt Date: Tue Jul 29 00:01:37 2025 -0700 Eliminate redundant vpextrq/vpinsrq when move TI to V4SI. r14-1902-g96c3539f2a3813 split TImode move with

[gcc r16-2624] Remove V64SFmode and V64SImode.

https://gcc.gnu.org/g:9d4a1931818a6141909d26dd4de50b4b099719fc commit r16-2624-g9d4a1931818a6141909d26dd4de50b4b099719fc Author: liuhongt Date: Mon Jul 28 20:01:54 2025 -0700 Remove V64SFmode and V64SImode. It's needed by avx5124vnniw/avx5124fmaps which have been removed by r1

[gcc r15-10163] Eliminate redundant vpextrq/vpinsrq when move TI to V4SI.

https://gcc.gnu.org/g:82cc62b51dcbc74298424c2e9540dd479ca5f26f commit r15-10163-g82cc62b51dcbc74298424c2e9540dd479ca5f26f Author: liuhongt Date: Tue Jul 29 00:01:37 2025 -0700 Eliminate redundant vpextrq/vpinsrq when move TI to V4SI. r14-1902-g96c3539f2a3813 split TImode move with

[gcc r14-11923] Eliminate redundant vpextrq/vpinsrq when move TI to V4SI.

https://gcc.gnu.org/g:c8eb4fcd40c2faef5dadbaa83abfcc6e058ee9f6 commit r14-11923-gc8eb4fcd40c2faef5dadbaa83abfcc6e058ee9f6 Author: liuhongt Date: Tue Jul 29 00:01:37 2025 -0700 Eliminate redundant vpextrq/vpinsrq when move TI to V4SI. r14-1902-g96c3539f2a3813 split TImode move with

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