[gcc r14-9344] RISC-V: Adjust vec unit-stride load/store costs.

https://gcc.gnu.org/g:9ae83078fe45d093bbaa02b8348f2407fe0c62d6 commit r14-9344-g9ae83078fe45d093bbaa02b8348f2407fe0c62d6 Author: Robin Dapp Date: Mon Jan 15 17:34:58 2024 +0100 RISC-V: Adjust vec unit-stride load/store costs. Scalar loads provide offset addressing while unit-strid

[gcc r14-9345] RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloads [PR114200].

https://gcc.gnu.org/g:59554a50be8ebbd52e8a6348a92110af182e1874 commit r14-9345-g59554a50be8ebbd52e8a6348a92110af182e1874 Author: Robin Dapp Date: Wed Mar 6 12:15:40 2024 +0100 RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloads [PR114200]. Three-operand instructions like

[gcc r14-9366] vect: Do not peel epilogue for partial vectors.

https://gcc.gnu.org/g:226043a4d8fb23c7fe7bf16e485b3cfaa094db21 commit r14-9366-g226043a4d8fb23c7fe7bf16e485b3cfaa094db21 Author: Robin Dapp Date: Wed Mar 6 16:54:35 2024 +0100 vect: Do not peel epilogue for partial vectors. r14-7036-gcbf569486b2dec added an epilogue vectorization

[gcc r15-638] internal-fn: Do not force vcond_mask operands to reg.

https://gcc.gnu.org/g:7ca35f2e430081d6ec91e910002f92d9713350fa commit r15-638-g7ca35f2e430081d6ec91e910002f92d9713350fa Author: Robin Dapp Date: Fri May 10 12:44:44 2024 +0200 internal-fn: Do not force vcond_mask operands to reg. In order to directly use constants this patch remov

[gcc r15-639] RISC-V: Add initial cost handling for segment loads/stores.

https://gcc.gnu.org/g:e0b9c8ad7098fb08a25a61fe17d4274dd73e5145 commit r15-639-ge0b9c8ad7098fb08a25a61fe17d4274dd73e5145 Author: Robin Dapp Date: Mon Feb 26 13:09:15 2024 +0100 RISC-V: Add initial cost handling for segment loads/stores. This patch makes segment loads and stores mor

[gcc r15-3119] RISC-V: Expand vec abs without masking.

https://gcc.gnu.org/g:c22d57cdc52d990eb7d353fa82c67882bc824d40 commit r15-3119-gc22d57cdc52d990eb7d353fa82c67882bc824d40 Author: Robin Dapp Date: Fri Aug 9 15:05:39 2024 +0200 RISC-V: Expand vec abs without masking. Standard abs synthesis during expand is max (a, -a). This ex

[gcc r15-3120] optabs-query: Use opt_machine_mode for smallest_int_mode_for_size [PR115495].

https://gcc.gnu.org/g:96fe95bac67c7303dc811c04f5e99cc959a7182a commit r15-3120-g96fe95bac67c7303dc811c04f5e99cc959a7182a Author: Robin Dapp Date: Tue Aug 20 14:02:09 2024 +0200 optabs-query: Use opt_machine_mode for smallest_int_mode_for_size [PR115495]. In get_best_extraction_in

[gcc r15-3282] RISC-V: Fix subreg of VLS modes larger than a vector [PR116086].

https://gcc.gnu.org/g:4ff4875a79ccb302dc2401c32fe0af2187b61b99 commit r15-3282-g4ff4875a79ccb302dc2401c32fe0af2187b61b99 Author: Robin Dapp Date: Tue Aug 27 10:25:34 2024 +0200 RISC-V: Fix subreg of VLS modes larger than a vector [PR116086]. When the source mode is potentially lar

[gcc r15-1861] RISC-V: Use tu policy for first-element vec_set [PR115725].

https://gcc.gnu.org/g:acc3b703c05debc6276451f9daae5d0ffc797eac commit r15-1861-gacc3b703c05debc6276451f9daae5d0ffc797eac Author: Robin Dapp Date: Mon Jul 1 13:37:17 2024 +0200 RISC-V: Use tu policy for first-element vec_set [PR115725]. This patch changes the tail policy for vmv.s.

[gcc r15-2300] RISC-V: Allow LICM hoist POLY_INT configuration code sequence

https://gcc.gnu.org/g:4cbbce045681c234387d8d56376ea179dc869229 commit r15-2300-g4cbbce045681c234387d8d56376ea179dc869229 Author: Juzhe-Zhong Date: Thu Feb 1 23:45:50 2024 +0800 RISC-V: Allow LICM hoist POLY_INT configuration code sequence Realize in recent benchmark evaluation (co

[gcc r15-2301] RISC-V: Error early with V and no M extension.

https://gcc.gnu.org/g:e589ffb6d78881572ddea21df0d9b6c2641d574d commit r15-2301-ge589ffb6d78881572ddea21df0d9b6c2641d574d Author: Robin Dapp Date: Wed Jul 24 09:08:00 2024 +0200 RISC-V: Error early with V and no M extension. For calculating the value of a poly_int at runtime we use

[gcc r14-9972] RISC-V: Add VLS to mask vec_extract [PR114668].

https://gcc.gnu.org/g:02cc8f3e68f9af96d484d9946ceaa9e3eed38151 commit r14-9972-g02cc8f3e68f9af96d484d9946ceaa9e3eed38151 Author: Robin Dapp Date: Mon Apr 15 12:44:56 2024 +0200 RISC-V: Add VLS to mask vec_extract [PR114668]. This adds the missing VLS modes to the mask extract expa

[gcc r15-2337] RISC-V: Work around bare apostrophe in error string.

https://gcc.gnu.org/g:3f2bf415b447a0f6bc424c688b06e1f5946688a0 commit r15-2337-g3f2bf415b447a0f6bc424c688b06e1f5946688a0 Author: Robin Dapp Date: Fri Jul 26 12:58:38 2024 +0200 RISC-V: Work around bare apostrophe in error string. An unquoted apostrophe slipped through when testing

[gcc r15-2649] RISC-V: Correct mode_idx attribute for viwalu wx variants [PR116149].

https://gcc.gnu.org/g:f15cd1802129454029f7fcc8ee3ddd56a86cdad8 commit r15-2649-gf15cd1802129454029f7fcc8ee3ddd56a86cdad8 Author: Robin Dapp Date: Wed Jul 31 16:54:03 2024 +0200 RISC-V: Correct mode_idx attribute for viwalu wx variants [PR116149]. In PR116149 we choose a wrong vect

[gcc r15-951] RISC-V: Do not allow v0 as dest when merging [PR115068].

https://gcc.gnu.org/g:a2fd0812a54cf51520f15e900df4cfb5874b75ed commit r15-951-ga2fd0812a54cf51520f15e900df4cfb5874b75ed Author: Robin Dapp Date: Mon May 13 13:49:57 2024 +0200 RISC-V: Do not allow v0 as dest when merging [PR115068]. This patch splits the vfw...wf pattern so we do

[gcc r15-952] RISC-V: Split vwadd.wx and vwsub.wx and add helpers.

https://gcc.gnu.org/g:9781885a624f3e29634d95c14cd10940cefb1a5a commit r15-952-g9781885a624f3e29634d95c14cd10940cefb1a5a Author: Robin Dapp Date: Thu May 16 12:43:43 2024 +0200 RISC-V: Split vwadd.wx and vwsub.wx and add helpers. vwadd.wx and vwsub.wx have the same problem vfwadd.w

[gcc r15-953] RISC-V: Add vwsll combine helpers.

https://gcc.gnu.org/g:af4bf422a699de0e7af5a26e02997d313e7301a6 commit r15-953-gaf4bf422a699de0e7af5a26e02997d313e7301a6 Author: Robin Dapp Date: Mon May 13 22:09:35 2024 +0200 RISC-V: Add vwsll combine helpers. This patch enables the usage of vwsll in autovec context by adding the

[gcc r15-954] RISC-V: Use widening shift for scatter/gather if applicable.

https://gcc.gnu.org/g:309ee005aa871286c8daccbce7586f82be347440 commit r15-954-g309ee005aa871286c8daccbce7586f82be347440 Author: Robin Dapp Date: Fri May 10 13:37:03 2024 +0200 RISC-V: Use widening shift for scatter/gather if applicable. With the zvbb extension we can emit a wideni

[gcc r15-955] RISC-V: Add vandn combine helper.

https://gcc.gnu.org/g:f48448276f29a3823827292c72b7fc8e9cd39e1e commit r15-955-gf48448276f29a3823827292c72b7fc8e9cd39e1e Author: Robin Dapp Date: Wed May 15 15:01:35 2024 +0200 RISC-V: Add vandn combine helper. This patch adds a combine pattern for vandn as well as tests for it.

[gcc r15-956] RISC-V: Add vector popcount, clz, ctz.

https://gcc.gnu.org/g:6fa4b0135439d64c0ea1816594d7dc830e836376 commit r15-956-g6fa4b0135439d64c0ea1816594d7dc830e836376 Author: Robin Dapp Date: Wed May 15 17:41:07 2024 +0200 RISC-V: Add vector popcount, clz, ctz. This patch adds the zvbb vcpop, vclz and vctz to the autovec machi

[gcc r15-957] RISC-V: Remove dead perm series code and document.

https://gcc.gnu.org/g:30cfdd6ff56972d9d1b9dbdd43a8333c85618775 commit r15-957-g30cfdd6ff56972d9d1b9dbdd43a8333c85618775 Author: Robin Dapp Date: Fri May 17 12:48:52 2024 +0200 RISC-V: Remove dead perm series code and document. With the introduction of shuffle_series_patterns the e

[gcc r15-1042] RISC-V: Introduce -mvector-strict-align.

https://gcc.gnu.org/g:68b0742a49de7122d5023f0bf46460ff2fb3e3dd commit r15-1042-g68b0742a49de7122d5023f0bf46460ff2fb3e3dd Author: Robin Dapp Date: Tue May 28 21:19:26 2024 +0200 RISC-V: Introduce -mvector-strict-align. this patch disables movmisalign by default and introduces t

[gcc r15-1043] check_GNU_style: Use raw strings.

https://gcc.gnu.org/g:03e1a7270314800eb33632f778401570e65345bd commit r15-1043-g03e1a7270314800eb33632f778401570e65345bd Author: Robin Dapp Date: Mon May 13 22:05:57 2024 +0200 check_GNU_style: Use raw strings. This silences some warnings when using check_GNU_style. contr

[gcc r15-1061] RISC-V: Regenerate opt urls.

https://gcc.gnu.org/g:037fc4d1012dc9d533862ef7e2c946249877dd71 commit r15-1061-g037fc4d1012dc9d533862ef7e2c946249877dd71 Author: Robin Dapp Date: Thu Jun 6 09:32:28 2024 +0200 RISC-V: Regenerate opt urls. I wasn't aware that I needed to regenerate the opt urls when adding an o

[gcc r15-1187] vect: Merge loop mask and cond_op mask in fold-left reduction [PR115382].

https://gcc.gnu.org/g:2b438a0d2aa80f051a09b245a58f643540d4004b commit r15-1187-g2b438a0d2aa80f051a09b245a58f643540d4004b Author: Robin Dapp Date: Fri Jun 7 14:36:41 2024 +0200 vect: Merge loop mask and cond_op mask in fold-left reduction [PR115382]. Currently we discard the cond-o

[gcc r15-4378] RISC-V: Use biggest_mode as mode for constants.

https://gcc.gnu.org/g:cc217a1ecb04c9234b2cce7ba3c27701a050e402 commit r15-4378-gcc217a1ecb04c9234b2cce7ba3c27701a050e402 Author: Robin Dapp Date: Tue Oct 15 12:10:48 2024 +0200 RISC-V: Use biggest_mode as mode for constants. In compute_nregs_for_mode we expect that the current var

[gcc r15-3829] RISC-V: Add more vector-vector extract cases.

https://gcc.gnu.org/g:be50c763a07893416419b82538f259f43e0773d4 commit r15-3829-gbe50c763a07893416419b82538f259f43e0773d4 Author: Robin Dapp Date: Tue Sep 3 17:53:34 2024 +0200 RISC-V: Add more vector-vector extract cases. This adds a V16SI -> V4SI and related i.e. "quartering" vec

[gcc r15-3828] RISC-V: Fix effective target check.

https://gcc.gnu.org/g:e45537f56250f19cdf2ec09a744c6b11170c1001 commit r15-3828-ge45537f56250f19cdf2ec09a744c6b11170c1001 Author: Robin Dapp Date: Fri Aug 30 14:35:08 2024 +0200 RISC-V: Fix effective target check. The return value is inverted in check_effective_target_rvv_zvl256b_o

[gcc r15-3830] RISC-V: testsuite: Fix SELECT_VL SLP fallout.

https://gcc.gnu.org/g:4bd3ccae58d40fad6bd99ed08ef4e1e4d70fefd0 commit r15-3830-g4bd3ccae58d40fad6bd99ed08ef4e1e4d70fefd0 Author: Robin Dapp Date: Thu Sep 19 05:08:47 2024 -0700 RISC-V: testsuite: Fix SELECT_VL SLP fallout. This fixes asm-scan fallout from r15-3712-g5e3a4a01785e2d

[gcc r15-5389] RISC-V: Add else operand to masked loads [PR115336].

https://gcc.gnu.org/g:b89273a049a76ffc29dd43a536ad329f0d994c05 commit r15-5389-gb89273a049a76ffc29dd43a536ad329f0d994c05 Author: Robin Dapp Date: Thu Aug 8 10:31:22 2024 +0200 RISC-V: Add else operand to masked loads [PR115336]. This patch adds else operands to masked loads. Curr

[gcc r15-5385] vect: Add maskload else value support.

https://gcc.gnu.org/g:634ae740f5a839df6567c58cfdcd32a3833c4626 commit r15-5385-g634ae740f5a839df6567c58cfdcd32a3833c4626 Author: Robin Dapp Date: Thu Aug 8 14:29:05 2024 +0200 vect: Add maskload else value support. This patch adds an else operand to vectorized masked load calls.

[gcc r15-5387] gcn: Add else operand to masked loads.

https://gcc.gnu.org/g:4a39addb4921ca1f7aa013835cd1351226e5e6b6 commit r15-5387-g4a39addb4921ca1f7aa013835cd1351226e5e6b6 Author: Robin Dapp Date: Thu Aug 8 10:31:05 2024 +0200 gcn: Add else operand to masked loads. This patch adds an undefined else operand to the masked loads.

[gcc r15-5386] aarch64: Add masked-load else operands.

https://gcc.gnu.org/g:a166a6ccdc6c3d6532a24ba3a2057a177ce44752 commit r15-5386-ga166a6ccdc6c3d6532a24ba3a2057a177ce44752 Author: Robin Dapp Date: Thu Aug 8 10:30:58 2024 +0200 aarch64: Add masked-load else operands. This adds zero else operands to masked loads and their intrinsics

[gcc r15-5384] tree-ifcvt: Add zero maskload else value.

https://gcc.gnu.org/g:6b6bd53619fd11bab3def8dee737711a7ee539ea commit r15-5384-g6b6bd53619fd11bab3def8dee737711a7ee539ea Author: Robin Dapp Date: Thu Aug 8 12:54:36 2024 +0200 tree-ifcvt: Add zero maskload else value. When predicating a load we implicitly assume that the else valu

[gcc r15-5382] docs: Document maskload else operand and behavior.

https://gcc.gnu.org/g:5214ddb464aab6c98b6eb6a267dcc9952f030d2f commit r15-5382-g5214ddb464aab6c98b6eb6a267dcc9952f030d2f Author: Robin Dapp Date: Thu Aug 8 10:32:25 2024 +0200 docs: Document maskload else operand and behavior. This patch amends the documentation for masked loads (

[gcc r15-5390] RISC-V: Add VLS modes to strided loads.

https://gcc.gnu.org/g:52a392b8b797d01a7b0b06c8f20b0bf8374d489e commit r15-5390-g52a392b8b797d01a7b0b06c8f20b0bf8374d489e Author: Robin Dapp Date: Mon Nov 4 15:34:50 2024 +0100 RISC-V: Add VLS modes to strided loads. This patch adds VLS modes to the strided load expanders.

[gcc r15-5388] i386: Add zero maskload else operand.

https://gcc.gnu.org/g:ebf30772415cfd3fa544fc7262b28b948591538f commit r15-5388-gebf30772415cfd3fa544fc7262b28b948591538f Author: Robin Dapp Date: Tue Nov 5 14:47:07 2024 +0100 i386: Add zero maskload else operand. gcc/ChangeLog: * config/i386/sse.md (maskload):

[gcc r15-5383] ifn: Add else-operand handling.

https://gcc.gnu.org/g:8f68d9cb7897df188f7dcd733d8c385f77fd8011 commit r15-5383-g8f68d9cb7897df188f7dcd733d8c385f77fd8011 Author: Robin Dapp Date: Thu Aug 8 10:54:35 2024 +0200 ifn: Add else-operand handling. This patch adds else-operand handling to the internal functions.

[gcc r15-5444] RISC-V: Load VLS perm indices directly from memory.

https://gcc.gnu.org/g:a18592e1c30f0f539c71fa632c49cb82008ec45a commit r15-5444-ga18592e1c30f0f539c71fa632c49cb82008ec45a Author: Robin Dapp Date: Thu Sep 26 11:56:08 2024 +0200 RISC-V: Load VLS perm indices directly from memory. Instead of loading the permutation indices and using

[gcc r15-5653] RISC-V: Ensure vtype for full-register moves [PR117544].

https://gcc.gnu.org/g:b82a5810e7bcc82b933e16f9067879b9d22b85c7 commit r15-5653-gb82a5810e7bcc82b933e16f9067879b9d22b85c7 Author: Robin Dapp Date: Thu Nov 21 14:49:53 2024 +0100 RISC-V: Ensure vtype for full-register moves [PR117544]. As discussed in PR117544 the VTYPE register is

[gcc r15-5652] genemit: Distribute evenly to files [PR111600].

https://gcc.gnu.org/g:2e6b3308af6ddf87925321ddd2d387bfd352e410 commit r15-5652-g2e6b3308af6ddf87925321ddd2d387bfd352e410 Author: Robin Dapp Date: Thu Nov 21 15:34:37 2024 +0100 genemit: Distribute evenly to files [PR111600]. currently we distribute insn patterns in genemit, partit

[gcc r15-5673] RISC-V: avlprop: Do not propagate VL from slidedown.

https://gcc.gnu.org/g:9c82afd42e7b5c3bdb849c66879138e59d8eb866 commit r15-5673-g9c82afd42e7b5c3bdb849c66879138e59d8eb866 Author: Robin Dapp Date: Mon Nov 25 12:40:53 2024 +0100 RISC-V: avlprop: Do not propagate VL from slidedown. In the following situation (found in the rvv/au

[gcc r15-6278] RISC-V: Fix compress shuffle pattern [PR117383].

https://gcc.gnu.org/g:ec870d3b5f378172006104bad674d7875463da18 commit r15-6278-gec870d3b5f378172006104bad674d7875463da18 Author: Robin Dapp Date: Wed Dec 11 20:48:30 2024 +0100 RISC-V: Fix compress shuffle pattern [PR117383]. This patch makes vcompress use the tail-undisturbed pol

[gcc r15-6277] RISC-V: Increase cost for vec_construct [PR118019].

https://gcc.gnu.org/g:ce199a952bfef3e27354a4586a17bc55274c1d3c commit r15-6277-gce199a952bfef3e27354a4586a17bc55274c1d3c Author: Robin Dapp Date: Fri Dec 13 11:23:03 2024 +0100 RISC-V: Increase cost for vec_construct [PR118019]. For a generic vec_construct from scalar elements we

[gcc r15-6279] vect: Do not try to duplicate_and_interleave one-element mode.

https://gcc.gnu.org/g:99eef0cfa56573c32b9c0a1e43519ee4300ac63f commit r15-6279-g99eef0cfa56573c32b9c0a1e43519ee4300ac63f Author: Robin Dapp Date: Fri Sep 6 16:04:03 2024 +0200 vect: Do not try to duplicate_and_interleave one-element mode. PR112694 shows that we try to create sub-v

[gcc r15-6280] docs: Fix [us]abd pattern name.

https://gcc.gnu.org/g:65c09538420ed820a24aac982a0299226b879d91 commit r15-6280-g65c09538420ed820a24aac982a0299226b879d91 Author: Robin Dapp Date: Thu Dec 12 11:46:32 2024 +0100 docs: Fix [us]abd pattern name. The uabd and sabd optab name is missing a 3 suffix (for its three ar

[gcc r15-6212] RISC-V: Add interleave pattern.

https://gcc.gnu.org/g:cff3050a4fbec323629563b87c9a83bf3e7be908 commit r15-6212-gcff3050a4fbec323629563b87c9a83bf3e7be908 Author: Robin Dapp Date: Wed Oct 16 22:39:08 2024 +0200 RISC-V: Add interleave pattern. This patch adds efficient handling of interleaving patterns like [0

[gcc r15-6210] RISC-V: Emit vector shift pattern for const_vector [PR117353].

https://gcc.gnu.org/g:cfdab86f20f6e77d9c8bf982989f78ef975c7611 commit r15-6210-gcfdab86f20f6e77d9c8bf982989f78ef975c7611 Author: Robin Dapp Date: Thu Dec 12 10:33:28 2024 +0100 RISC-V: Emit vector shift pattern for const_vector [PR117353]. In PR117353 and PR117878 we expand a cons

[gcc r15-6211] RISC-V: Add slide to perm_const strategies.

https://gcc.gnu.org/g:71bfc8c33e63f4a566079d34ed3bc98f45133e96 commit r15-6211-g71bfc8c33e63f4a566079d34ed3bc98f45133e96 Author: Robin Dapp Date: Mon Sep 16 22:22:14 2024 +0200 RISC-V: Add slide to perm_const strategies. This patch adds a shuffle_slide_patterns to expand_vec_perm_

[gcc r15-6213] RISC-V: Add even/odd vec_perm_const pattern.

https://gcc.gnu.org/g:528567a7b1589735408eaa133206a0683162188e commit r15-6213-g528567a7b1589735408eaa133206a0683162188e Author: Robin Dapp Date: Thu Oct 17 11:33:19 2024 +0200 RISC-V: Add even/odd vec_perm_const pattern. This adds handling for even/odd patterns. gcc/Chan

[gcc r15-6214] RISC-V: Improve slide1up pattern.

https://gcc.gnu.org/g:12a5ab146110631edffcd307a0c10773160f2723 commit r15-6214-g12a5ab146110631edffcd307a0c10773160f2723 Author: Robin Dapp Date: Sat Nov 16 15:13:09 2024 +0100 RISC-V: Improve slide1up pattern. This patch adds a second variant to implement the extract/slide1up

[gcc r15-6223] genrecog: Split into separate partitions [PR111600].

https://gcc.gnu.org/g:6dcfe8743134936db17ffdfd0a5102a87338f494 commit r15-6223-g6dcfe8743134936db17ffdfd0a5102a87338f494 Author: Robin Dapp Date: Tue Nov 26 14:44:17 2024 +0100 genrecog: Split into separate partitions [PR111600]. Hi, this patch makes genrecog split its ou

[gcc r15-7110] RISC-V: Unbreak bootstrap.

https://gcc.gnu.org/g:e324619281239bb513840600436b735dfbd32416 commit r15-7110-ge324619281239bb513840600436b735dfbd32416 Author: Robin Dapp Date: Tue Jan 21 18:07:41 2025 +0100 RISC-V: Unbreak bootstrap. This fixes a wrong format specifier and an unused variable which should r

[gcc r15-7236] RISC-V: testsuite: Fix gather_load_64-12-zvbb.c

https://gcc.gnu.org/g:c0c2304e19be438a64841f6a3c56b134ba02d9a6 commit r15-7236-gc0c2304e19be438a64841f6a3c56b134ba02d9a6 Author: Robin Dapp Date: Wed Jan 22 16:19:49 2025 +0100 RISC-V: testsuite: Fix gather_load_64-12-zvbb.c The test fails with _zvfh because we vectorize more. Ju

[gcc r15-7235] RISC-V: Disable two-source permutes for now [PR117173].

https://gcc.gnu.org/g:006b4e45f3ab169a47146b31d9721c79098236ac commit r15-7235-g006b4e45f3ab169a47146b31d9721c79098236ac Author: Robin Dapp Date: Thu Oct 17 18:39:16 2024 +0200 RISC-V: Disable two-source permutes for now [PR117173]. After testing on the BPI (4.2% improvement for x

[gcc r15-7237] RISC-V: testsuite: Fix reduc-8.c and reduc-9.c

https://gcc.gnu.org/g:f7dc4fd62ce4d9287988892b1e94bbdd0ca1c8fa commit r15-7237-gf7dc4fd62ce4d9287988892b1e94bbdd0ca1c8fa Author: Robin Dapp Date: Wed Jan 22 18:05:44 2025 +0100 RISC-V: testsuite: Fix reduc-8.c and reduc-9.c In both tests we expect a VEC_SHL_INSERT expression but w

[gcc r15-6891] match: Keep conditional in simplification to constant [PR118140].

https://gcc.gnu.org/g:14cb0610559fa33f211e1546260458496fdc5e71 commit r15-6891-g14cb0610559fa33f211e1546260458496fdc5e71 Author: Robin Dapp Date: Fri Dec 27 17:29:25 2024 +0100 match: Keep conditional in simplification to constant [PR118140]. In PR118140 we simplify _if

[gcc r15-6892] RISC-V: Fix vsetvl compatibility predicate [PR118154].

https://gcc.gnu.org/g:e5e9e50fc6816713d012f1d96ae308a0946d5a14 commit r15-6892-ge5e9e50fc6816713d012f1d96ae308a0946d5a14 Author: Robin Dapp Date: Thu Jan 9 20:45:10 2025 +0100 RISC-V: Fix vsetvl compatibility predicate [PR118154]. In PR118154 we emit strided stores but the first o

[gcc r14-11210] match: Keep conditional in simplification to constant [PR118140].

https://gcc.gnu.org/g:9b8488f662b070933d0427df22811bf1eaac661e commit r14-11210-g9b8488f662b070933d0427df22811bf1eaac661e Author: Robin Dapp Date: Fri Dec 27 17:29:25 2024 +0100 match: Keep conditional in simplification to constant [PR118140]. In PR118140 we simplify _i

[gcc r15-7687] vect: Use original LHS type for gather pattern [PR118950].

https://gcc.gnu.org/g:f3d4208e798afafcba5246334004e9646e390681 commit r15-7687-gf3d4208e798afafcba5246334004e9646e390681 Author: Robin Dapp Date: Fri Feb 21 07:19:40 2025 +0100 vect: Use original LHS type for gather pattern [PR118950]. In PR118950 we do not zero masked elements in

[gcc r15-7688] RISC-V: Include pattern stmts for dynamic LMUL computation [PR114516].

https://gcc.gnu.org/g:6be1b9e94d9a2ead15e3625e833f1e34503ab803 commit r15-7688-g6be1b9e94d9a2ead15e3625e833f1e34503ab803 Author: Robin Dapp Date: Fri Feb 21 17:08:16 2025 +0100 RISC-V: Include pattern stmts for dynamic LMUL computation [PR114516]. When scanning for program points,

[gcc r15-7608] RISC-V: Fix ratio in vsetvl fuse rule [PR115703].

https://gcc.gnu.org/g:44d4a1086d965fb5280daf65c7c4a253ad6cc8a1 commit r15-7608-g44d4a1086d965fb5280daf65c7c4a253ad6cc8a1 Author: Robin Dapp Date: Thu Feb 6 14:43:17 2025 +0100 RISC-V: Fix ratio in vsetvl fuse rule [PR115703]. In PR115703 we fuse two vsetvls: Fuse curr

[gcc r15-8021] RISC-V: Adjust LMUL when using maximum SEW [PR117955].

https://gcc.gnu.org/g:f043ef2b6a59088b16a269b55f09023f76c92e32 commit r15-8021-gf043ef2b6a59088b16a269b55f09023f76c92e32 Author: Robin Dapp Date: Tue Feb 25 12:55:08 2025 +0100 RISC-V: Adjust LMUL when using maximum SEW [PR117955]. When merging two vsetvls that both only demand "S

[gcc r15-8022] RISC-V: Do not delete fused vsetvl if it has uses [PR119115].

https://gcc.gnu.org/g:77ef91d7159613c0cfc2920ddd5a32952c61ff5b commit r15-8022-g77ef91d7159613c0cfc2920ddd5a32952c61ff5b Author: Robin Dapp Date: Wed Mar 5 18:16:57 2025 +0100 RISC-V: Do not delete fused vsetvl if it has uses [PR119115]. In PR119115 we end up with an orphaned

[gcc r15-8084] RISC-V: Mask values before initializing bitmask vector [PR119114].

https://gcc.gnu.org/g:b58a0af4e2e28b395a3cb4b7283f16f05c0cf3c8 commit r15-8084-gb58a0af4e2e28b395a3cb4b7283f16f05c0cf3c8 Author: Robin Dapp Date: Tue Mar 11 14:30:48 2025 +0100 RISC-V: Mask values before initializing bitmask vector [PR119114]. In the somewhat convoluted vector cod