https://gcc.gnu.org/g:f7dc4fd62ce4d9287988892b1e94bbdd0ca1c8fa
commit r15-7237-gf7dc4fd62ce4d9287988892b1e94bbdd0ca1c8fa
Author: Robin Dapp <rd...@ventanamicro.com>
Date: Wed Jan 22 18:05:44 2025 +0100
RISC-V: testsuite: Fix reduc-8.c and reduc-9.c
In both tests we expect a VEC_SHL_INSERT expression but we now add the
initial value at the end. Just remove that scan check.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/reduc/reduc-8.c: Remove
VEC_SHL_INSERT check.
* gcc.target/riscv/rvv/autovec/reduc/reduc-9.c: Ditto.
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c | 1 -
gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c
index fe47aa3648dd..518f0c33cc4e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c
@@ -12,5 +12,4 @@ add_loop (int *x, int n, int res)
return res;
}
-/* { dg-final { scan-tree-dump-times "VEC_SHL_INSERT" 1 "optimized" } } */
/* { dg-final { scan-assembler-times
{vslide1up\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c
index 6630d3027210..a5bb8dcccb81 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c
@@ -12,5 +12,4 @@ add_loop (float *x, int n, float res)
return res;
}
-/* { dg-final { scan-tree-dump-times "VEC_SHL_INSERT" 1 "optimized" } } */
/* { dg-final { scan-assembler-times
{vfslide1up\.vf\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
