[gcc r15-3441] Zen5 tuning part 5: update instruction latencies in x86-tune-costs

https://gcc.gnu.org/g:4292297a0f938ffc953422fa246ff00fe345fe3d commit r15-3441-g4292297a0f938ffc953422fa246ff00fe345fe3d Author: Jan Hubicka Date: Wed Sep 4 09:19:08 2024 +0200 Zen5 tuning part 5: update instruction latencies in x86-tune-costs there is nothing exciting in this pat

[gcc r15-3442] Also lower SLP grouped loads with just one consumer

https://gcc.gnu.org/g:7164d982663738c255a1a71a5d4f38dc51c2a3cb commit r15-3442-g7164d982663738c255a1a71a5d4f38dc51c2a3cb Author: Richard Biener Date: Mon Sep 2 15:00:05 2024 +0200 Also lower SLP grouped loads with just one consumer This makes sure to produce interleaving schemes o

[gcc r15-3443] rust: avoid clobbering LIBS

https://gcc.gnu.org/g:da3a2985fff39ee8ec1b9f48699e3b8197e439e6 commit r15-3443-gda3a2985fff39ee8ec1b9f48699e3b8197e439e6 Author: Marc Poulhiès Date: Mon Aug 5 17:41:17 2024 +0200 rust: avoid clobbering LIBS Save LIBS around calls to AC_SEARCH_LIBS to avoid clobbering $LIBS.

[gcc r15-3444] Add 'gcc.target/nvptx/alias-weak-1.c'

https://gcc.gnu.org/g:2267d254eb6ad782cef7b462f2bb2128bc8ace30 commit r15-3444-g2267d254eb6ad782cef7b462f2bb2128bc8ace30 Author: Thomas Schwinge Date: Wed Sep 4 09:58:32 2024 +0200 Add 'gcc.target/nvptx/alias-weak-1.c' ... testing for the GCC/nvptx "weak alias definitions not supp

[gcc r15-3445] Add 'gcc.target/nvptx/alias-to-alias-1.c'

https://gcc.gnu.org/g:a89321c890b96c583671b73fc802e87545e4a2b1 commit r15-3445-ga89321c890b96c583671b73fc802e87545e4a2b1 Author: Thomas Schwinge Date: Wed Sep 4 09:44:33 2024 +0200 Add 'gcc.target/nvptx/alias-to-alias-1.c' ... similar to alias to alias usage in 'libgomp.c-c++-comm

[gcc r15-3446] nvptx: Specify '-mno-alias' for 'gcc.dg/pr60797.c' [PR60797, PR104957]

https://gcc.gnu.org/g:b9be3113a9365e8380397abb23abc71f049cf4f1 commit r15-3446-gb9be3113a9365e8380397abb23abc71f049cf4f1 Author: Thomas Schwinge Date: Sun Jul 21 22:23:40 2024 +0200 nvptx: Specify '-mno-alias' for 'gcc.dg/pr60797.c' [PR60797, PR104957] 2014 Subversion r209299 (Git

[gcc r15-3447] Document 'pass_postreload' vs. 'pass_late_compilation'

https://gcc.gnu.org/g:438381ef759ee8b5b04c5723a8334354ba2a30e5 commit r15-3447-g438381ef759ee8b5b04c5723a8334354ba2a30e5 Author: Thomas Schwinge Date: Fri Jun 28 16:04:18 2024 +0200 Document 'pass_postreload' vs. 'pass_late_compilation' See Subversion r217124 (Git commit 433e41643

[gcc r15-3448] Fix gimple_debug_cfg declaration

https://gcc.gnu.org/g:347a953d855c6b246b1604bdf4728f615cb471b6 commit r15-3448-g347a953d855c6b246b1604bdf4728f615cb471b6 Author: Frederik Harwath Date: Tue Nov 16 16:08:40 2021 +0100 Fix gimple_debug_cfg declaration Silence a warning. The argument type did not match the definition

[gcc r15-3449] Fix branch prediction dump message

https://gcc.gnu.org/g:35e4414bac06927387fb7a6fe10b373e766da1c1 commit r15-3449-g35e4414bac06927387fb7a6fe10b373e766da1c1 Author: Frederik Harwath Date: Tue Nov 16 16:13:51 2021 +0100 Fix branch prediction dump message Instead of, for instance, "Loop got predicted 1 to iterate 10 t

[gcc r14-10629] Update LDPT_REGISTER_CLAIM_FILE_HOOK_V2 linker plugin hook

https://gcc.gnu.org/g:66eb7b752ab61c02348d6af10945af3ff92b6d77 commit r14-10629-g66eb7b752ab61c02348d6af10945af3ff92b6d77 Author: H.J. Lu Date: Wed Aug 21 07:25:25 2024 -0700 Update LDPT_REGISTER_CLAIM_FILE_HOOK_V2 linker plugin hook This hook allows the BFD linker plugin to disti

[gcc r14-10630] lto: Don't check obj.found for offload section

https://gcc.gnu.org/g:0562522e1290da08bc5a89182b9ae80c3cc9d1db commit r14-10630-g0562522e1290da08bc5a89182b9ae80c3cc9d1db Author: H.J. Lu Date: Fri Aug 23 05:36:45 2024 -0700 lto: Don't check obj.found for offload section obj.found is the number of LTO symbols. We should include

[gcc r15-3450] nvptx: Use 'enum ptx_version', 'enum ptx_isa' instead of 'int'

https://gcc.gnu.org/g:fee2fbedbb43ad7a017a33ed2b820be79b75e7e5 commit r15-3450-gfee2fbedbb43ad7a017a33ed2b820be79b75e7e5 Author: Thomas Schwinge Date: Mon Jul 22 10:49:16 2024 +0200 nvptx: Use 'enum ptx_version', 'enum ptx_isa' instead of 'int' This allows getting rid of the respe

[gcc r15-3451] Use dg-additional-options for gfortran.dg/vect/vect-8.f90 and RISC-V

https://gcc.gnu.org/g:284feaa809294995d6c133b8d002850a069c1ded commit r15-3451-g284feaa809294995d6c133b8d002850a069c1ded Author: Richard Biener Date: Wed Sep 4 16:00:00 2024 +0200 Use dg-additional-options for gfortran.dg/vect/vect-8.f90 and RISC-V r14-9122-g67a29f99cc8138 disable

[gcc r15-3452] object-size: Use simple_dce_from_worklist in object-size pass

https://gcc.gnu.org/g:97e011a472e16ddab67d7374ee9c3db040b62798 commit r15-3452-g97e011a472e16ddab67d7374ee9c3db040b62798 Author: Andrew Pinski Date: Tue Sep 3 12:48:46 2024 -0700 object-size: Use simple_dce_from_worklist in object-size pass While trying to see if there was a way t

[gcc r15-3453] coros: mark .CO_YIELD as LEAF [PR106973]

https://gcc.gnu.org/g:7b7ad3f4b2455072f42e7884b93fd96ebb920bc8 commit r15-3453-g7b7ad3f4b2455072f42e7884b93fd96ebb920bc8 Author: Arsen Arsenović Date: Tue Sep 3 17:14:13 2024 +0200 coros: mark .CO_YIELD as LEAF [PR106973] We rely on .CO_YIELD calls being followed by an assignment

[gcc r15-3454] c++: add a testcase for [PR 108620]

https://gcc.gnu.org/g:858918ef4233c837ab85819ad159bf452df3a7fb commit r15-3454-g858918ef4233c837ab85819ad159bf452df3a7fb Author: Arsen Arsenović Date: Tue Sep 3 20:58:55 2024 +0200 c++: add a testcase for [PR 108620] Fixed by r15-2540-g32e678b2ed7521. Add a testcase, as the origi

[gcc(refs/users/meissner/heads/work177-tar)] Add support for the TAR register.

https://gcc.gnu.org/g:5c2283f478e908718024e5b3b53dc8c4db3a8fe9 commit 5c2283f478e908718024e5b3b53dc8c4db3a8fe9 Author: Michael Meissner Date: Wed Sep 4 11:36:25 2024 -0400 Add support for the TAR register. 2024-09-04 Michael Meissner gcc/ * config/rs60

[gcc(refs/users/meissner/heads/work177-tar)] Remove SPR alternatives for move insns.

https://gcc.gnu.org/g:a719aa37a9ddcea20ef9da9c2097ee48465da758 commit a719aa37a9ddcea20ef9da9c2097ee48465da758 Author: Michael Meissner Date: Wed Sep 4 11:38:07 2024 -0400 Remove SPR alternatives for move insns. 2024-09-04 Michael Meissner * config/rs6000/rs600

[gcc(refs/users/meissner/heads/work177-tar)] Update ChangeLog.*

https://gcc.gnu.org/g:ca08fa1266ef9d4678a9ee5b094a06c4f753bda9 commit ca08fa1266ef9d4678a9ee5b094a06c4f753bda9 Author: Michael Meissner Date: Wed Sep 4 11:40:35 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 83 ++- 1 file

[gcc(refs/users/meissner/heads/work177-libs)] Do not build IEEE 128-bit libgfortran support if VSX is not available.

https://gcc.gnu.org/g:b766e0eb3bd24ca74f54cddc957db0b3ba84187e commit b766e0eb3bd24ca74f54cddc957db0b3ba84187e Author: Michael Meissner Date: Wed Sep 4 11:29:29 2024 -0400 Do not build IEEE 128-bit libgfortran support if VSX is not available. If you build a little endian compiler

[gcc(refs/users/meissner/heads/work177-libs)] Do not build IEEE 128-bit libstdc++ support if VSX is not available.

https://gcc.gnu.org/g:61b479aadbe46f39409f8f3996e3192adf60b66d commit 61b479aadbe46f39409f8f3996e3192adf60b66d Author: Michael Meissner Date: Wed Sep 4 11:30:57 2024 -0400 Do not build IEEE 128-bit libstdc++ support if VSX is not available. If you build a little endian compiler an

[gcc(refs/users/meissner/heads/work177-libs)] Do not build IEEE 128-bit libstdc++ support if VSX is not available.

https://gcc.gnu.org/g:3696abc890a0e9acbd4e93c688d0e238c011ee76 commit 3696abc890a0e9acbd4e93c688d0e238c011ee76 Author: Michael Meissner Date: Wed Sep 4 11:31:56 2024 -0400 Do not build IEEE 128-bit libstdc++ support if VSX is not available. If you build a little endian compiler an

[gcc(refs/users/meissner/heads/work177-libs)] Do not add -mvsx when testing the float128 support.

https://gcc.gnu.org/g:db95aceee0bf62edcb1fa34e5c61279fa09ed158 commit db95aceee0bf62edcb1fa34e5c61279fa09ed158 Author: Michael Meissner Date: Wed Sep 4 11:33:00 2024 -0400 Do not add -mvsx when testing the float128 support. Currently, we add -mvsx when building the float128 suppor

[gcc(refs/users/meissner/heads/work177-libs)] Update ChangeLog.*

https://gcc.gnu.org/g:fde55641b666e342f2de9889b930fb8bbec4d691 commit fde55641b666e342f2de9889b930fb8bbec4d691 Author: Michael Meissner Date: Wed Sep 4 11:44:02 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.libs | 210 - 1 file

[gcc(refs/users/meissner/heads/work177-dmf)] Use vector pair load/store for memcpy with -mcpu=future

https://gcc.gnu.org/g:9713c43be031a884541dc63e6c6efae74f7da3ce commit 9713c43be031a884541dc63e6c6efae74f7da3ce Author: Michael Meissner Date: Wed Sep 4 11:48:12 2024 -0400 Use vector pair load/store for memcpy with -mcpu=future In the development for the power10 processor, GCC did

[gcc(refs/users/meissner/heads/work177-dmf)] RFC2653-Add wD constraint.

https://gcc.gnu.org/g:76f0343e31fc5da729986de72551d8622aafd728 commit 76f0343e31fc5da729986de72551d8622aafd728 Author: Michael Meissner Date: Wed Sep 4 11:49:07 2024 -0400 RFC2653-Add wD constraint. This patch adds a new constraint ('wD') that matches the accumulator registers

[gcc(refs/users/meissner/heads/work177-dmf)] RFC2653-Add support for dense math registers.

https://gcc.gnu.org/g:0ad27476f30202855d64376550757839733f533c commit 0ad27476f30202855d64376550757839733f533c Author: Michael Meissner Date: Wed Sep 4 11:50:40 2024 -0400 RFC2653-Add support for dense math registers. The MMA subsystem added the notion of accumulator registers as

[gcc(refs/users/meissner/heads/work177-dmf)] RFC2653-PowerPC: Switch to dense math names for all MMA operations.

https://gcc.gnu.org/g:e0b9b958eef1fa1bb51267d4971bb0416fbe commit e0b9b958eef1fa1bb51267d4971bb0416fbe Author: Michael Meissner Date: Wed Sep 4 11:51:51 2024 -0400 RFC2653-PowerPC: Switch to dense math names for all MMA operations. This patch changes the assembler instruct

[gcc(refs/users/meissner/heads/work177-dmf)] RFC2653-PowerPC: Add support for 1, 024 bit DMR registers.

https://gcc.gnu.org/g:62146c78439db4835ad918255a08e57f41de47ce commit 62146c78439db4835ad918255a08e57f41de47ce Author: Michael Meissner Date: Wed Sep 4 11:53:39 2024 -0400 RFC2653-PowerPC: Add support for 1,024 bit DMR registers. This patch is a prelimianry patch to add the full 1

[gcc(refs/users/meissner/heads/work177-dmf)] RFC2653-Add dense math test for new instruction names.

https://gcc.gnu.org/g:d753057babaa0596db1ae5cf9d8641311644b8da commit d753057babaa0596db1ae5cf9d8641311644b8da Author: Michael Meissner Date: Wed Sep 4 11:52:44 2024 -0400 RFC2653-Add dense math test for new instruction names. 2024-09-04 Michael Meissner gcc/testsuite

[gcc(refs/users/meissner/heads/work177-dmf)] RFC2677-Add xvrlw support.

https://gcc.gnu.org/g:f75816fc6e800be9339c0337ebad3a70011b8cfa commit f75816fc6e800be9339c0337ebad3a70011b8cfa Author: Michael Meissner Date: Wed Sep 4 12:03:06 2024 -0400 RFC2677-Add xvrlw support. 2024-09-04 Michael Meissner gcc/ * config/rs6000/alti

[gcc(refs/users/meissner/heads/work177-dmf)] RFC2655-Add saturating subtract built-ins.

https://gcc.gnu.org/g:7a50bae26c4b3fb169869b9410d136b4395aa7d0 commit 7a50bae26c4b3fb169869b9410d136b4395aa7d0 Author: Michael Meissner Date: Wed Sep 4 12:00:55 2024 -0400 RFC2655-Add saturating subtract built-ins. This patch adds support for a saturating subtract built-in functio

[gcc(refs/users/meissner/heads/work177-dmf)] RFC2656-Support load/store vector with right length.

https://gcc.gnu.org/g:1f58c992798e8c14b5733ced7c8a284cfa6962fe commit 1f58c992798e8c14b5733ced7c8a284cfa6962fe Author: Michael Meissner Date: Wed Sep 4 11:59:59 2024 -0400 RFC2656-Support load/store vector with right length. This patch adds support for new instructions that may be

[gcc(refs/users/meissner/heads/work177-dmf)] RFC2686-Add paddis support.

https://gcc.gnu.org/g:b41c5c62dca5c1d8e945832b2c4583a59791a795 commit b41c5c62dca5c1d8e945832b2c4583a59791a795 Author: Michael Meissner Date: Wed Sep 4 12:02:12 2024 -0400 RFC2686-Add paddis support. 2024-09-04 Michael Meissner gcc/ * config/rs6000/con

[gcc(refs/users/meissner/heads/work177-dmf)] Update ChangeLog.*

https://gcc.gnu.org/g:9df39fe1e59bee61ab222bd5111f3e222d013c97 commit 9df39fe1e59bee61ab222bd5111f3e222d013c97 Author: Michael Meissner Date: Wed Sep 4 12:06:41 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.dmf | 449 +- 1 file

[gcc r15-3455] c++: noexcept and pointer to member function type [PR113108]

https://gcc.gnu.org/g:c755c7a32590e2eef5a8b062b9756c1513910246 commit r15-3455-gc755c7a32590e2eef5a8b062b9756c1513910246 Author: Marek Polacek Date: Tue Sep 3 13:04:09 2024 -0400 c++: noexcept and pointer to member function type [PR113108] We ICE in nothrow_spec_p because it got a

[gcc r15-3456] c++: cleanup coerce_template_template_parm

https://gcc.gnu.org/g:dedf453477aa966493541a484b2d4ee5a17e5b61 commit r15-3456-gdedf453477aa966493541a484b2d4ee5a17e5b61 Author: Marek Polacek Date: Wed Sep 4 13:43:52 2024 -0400 c++: cleanup coerce_template_template_parm This function could use some sprucing up. gcc/cp/C

[gcc r15-3457] [RISC-V] Fix scan test output after recent path-splitting changes

https://gcc.gnu.org/g:0455e85e4eda7d80bda967914d634fe5b71b7ffc commit r15-3457-g0455e85e4eda7d80bda967914d634fe5b71b7ffc Author: Jeff Law Date: Wed Sep 4 12:07:09 2024 -0600 [RISC-V] Fix scan test output after recent path-splitting changes The recent path splitting changes from An

[gcc r14-10631] aarch64: Refactor check_required_extensions

https://gcc.gnu.org/g:c6e04d1f92fc3b4215e7c179da5d4a51356f69a8 commit r14-10631-gc6e04d1f92fc3b4215e7c179da5d4a51356f69a8 Author: Andrew Carlotti Date: Tue Aug 13 16:15:11 2024 +0100 aarch64: Refactor check_required_extensions Replace TARGET_GENERAL_REGS_ONLY check with an explici

[gcc r14-10632] aarch64: Move check_required_extensions

https://gcc.gnu.org/g:422c3f1965d76a541385bdc419a4e1c46f007525 commit r14-10632-g422c3f1965d76a541385bdc419a4e1c46f007525 Author: Andrew Carlotti Date: Tue Jul 18 16:40:58 2023 +0100 aarch64: Move check_required_extensions Move SVE extension checking functionality to aarch64-built

[gcc r14-10633] aarch64: Fix tme intrinsic availability

https://gcc.gnu.org/g:0a3a0d4a5e32e9b914b5c5cc283ee485adc6cd11 commit r14-10633-g0a3a0d4a5e32e9b914b5c5cc283ee485adc6cd11 Author: Andrew Carlotti Date: Thu Oct 26 15:43:44 2023 +0100 aarch64: Fix tme intrinsic availability The availability of tme intrinsics was previously gated at

[gcc r14-10634] aarch64: Fix memtag intrinsic availability

https://gcc.gnu.org/g:8485606056ed3ca0d0acf6e0d943975e9173e7cd commit r14-10634-g8485606056ed3ca0d0acf6e0d943975e9173e7cd Author: Andrew Carlotti Date: Tue Jul 18 20:09:38 2023 +0100 aarch64: Fix memtag intrinsic availability The availability of memtag intrinsics and data types we

[gcc r14-10635] aarch64: Fix ls64 intrinsic availability

https://gcc.gnu.org/g:9899be7d5380c732b56ba155d4a9e192a2c483b1 commit r14-10635-g9899be7d5380c732b56ba155d4a9e192a2c483b1 Author: Andrew Carlotti Date: Thu Oct 26 15:45:15 2023 +0100 aarch64: Fix ls64 intrinsic availability The availability of ls64 intrinsics and data types were d

[gcc r15-3458] Check DECL_NAMELESS in modified_type_die

https://gcc.gnu.org/g:5326306e7d9d36eccc2c2f02e1357818625f057b commit r15-3458-g5326306e7d9d36eccc2c2f02e1357818625f057b Author: Tom Tromey Date: Thu Aug 29 13:23:18 2024 -0600 Check DECL_NAMELESS in modified_type_die While working on a patch to the Ada compiler, I found a spot in

[gcc r14-10636] libstdc++: Fix std::variant to reject array types [PR116381]

https://gcc.gnu.org/g:3b8a67b0cfc072f027eab24fb72d48d10cc890b4 commit r14-10636-g3b8a67b0cfc072f027eab24fb72d48d10cc890b4 Author: Jonathan Wakely Date: Tue Aug 20 16:52:22 2024 +0100 libstdc++: Fix std::variant to reject array types [PR116381] For the backport, rejecting array typ

[gcc r14-10638] libstdc++: Specialize std::disable_sized_sentinel_for for std::move_iterator [PR116549]

https://gcc.gnu.org/g:ee37d750262579a81799c5b56fe1ab936a840120 commit r14-10638-gee37d750262579a81799c5b56fe1ab936a840120 Author: Jonathan Wakely Date: Mon Sep 2 11:29:13 2024 +0100 libstdc++: Specialize std::disable_sized_sentinel_for for std::move_iterator [PR116549] LWG 3736 a

[gcc r14-10637] libstdc++: Add missing feature-test macro in various headers

https://gcc.gnu.org/g:469602619d32c24382c6f1c3e3d95c3db606c770 commit r14-10637-g469602619d32c24382c6f1c3e3d95c3db606c770 Author: Dhruv Chawla Date: Mon Aug 26 11:09:19 2024 +0530 libstdc++: Add missing feature-test macro in various headers version.syn#2 requires various headers t

[gcc r14-10639] libstdc++: Fix fs::hard_link_count behaviour on MinGW [PR113663]

https://gcc.gnu.org/g:ec1bcd176339d43fd1ab3211f65915824ba1f26b commit r14-10639-gec1bcd176339d43fd1ab3211f65915824ba1f26b Author: Lennox Shou Hao Ho Date: Mon Jul 29 21:09:27 2024 +0100 libstdc++: Fix fs::hard_link_count behaviour on MinGW [PR113663] std::filesystem::hard_link_cou

[gcc r14-10641] libstdc++: Fix error handling in fs::hard_link_count for Windows

https://gcc.gnu.org/g:a054ba563bde3dc834c5efac72b91c2803e4e289 commit r14-10641-ga054ba563bde3dc834c5efac72b91c2803e4e289 Author: Jonathan Wakely Date: Mon Sep 2 12:16:49 2024 +0100 libstdc++: Fix error handling in fs::hard_link_count for Windows The recent change to use auto_win_

[gcc r14-10640] libstdc++: Fix overwriting files with fs::copy_file on Windows

https://gcc.gnu.org/g:35c98149a5c7af9159fa7615d8d827b3aaa3cc97 commit r14-10640-g35c98149a5c7af9159fa7615d8d827b3aaa3cc97 Author: Jonathan Wakely Date: Tue Jul 30 10:55:55 2024 +0100 libstdc++: Fix overwriting files with fs::copy_file on Windows There are no inode numbers on Windo

[gcc r15-3459] [PATCH 1/3] RISC-V: Improve codegen for negative repeating large constants

https://gcc.gnu.org/g:cbea72b265e4c9d1a595bd3ecd11b325021925d0 commit r15-3459-gcbea72b265e4c9d1a595bd3ecd11b325021925d0 Author: Raphael Moreira Zinsly Date: Wed Sep 4 17:21:24 2024 -0600 [PATCH 1/3] RISC-V: Improve codegen for negative repeating large constants Improve handling o

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Fix mixed input kind permute optimization

https://gcc.gnu.org/g:ad83da212ba5a5e27484fe7a147a28294fab8829 commit ad83da212ba5a5e27484fe7a147a28294fab8829 Author: Richard Biener Date: Tue May 21 19:15:33 2024 +0200 Fix mixed input kind permute optimization When change_vec_perm_layout runs into a permute combining two no

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3

https://gcc.gnu.org/g:019b3585afb077022b1463dd7e786bec472ada31 commit 019b3585afb077022b1463dd7e786bec472ada31 Author: Pan Li Date: Tue Aug 27 14:37:01 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3 This patch would like to add test cases for the unsigned

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 4

https://gcc.gnu.org/g:51aee40c9d5d97b45d7d96781e1f43c9100702f6 commit 51aee40c9d5d97b45d7d96781e1f43c9100702f6 Author: Pan Li Date: Tue Aug 27 15:14:40 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 4 This patch would like to add test cases for the unsigned

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add missing mode_idx for vrol and vror

https://gcc.gnu.org/g:1e62adc9cd6aa61948b106b1476fdf86eee7f3e0 commit 1e62adc9cd6aa61948b106b1476fdf86eee7f3e0 Author: Kito Cheng Date: Tue Aug 27 21:27:02 2024 +0800 RISC-V: Add missing mode_idx for vrol and vror We add pattern for vector rotate, but seems like we forgot adding

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Partial: Just the testsuite bits.

https://gcc.gnu.org/g:a4b71f89a6e6090d775ab34e7ce365e8d8e8 commit a4b71f89a6e6090d775ab34e7ce365e8d8e8 Author: Pan Li Date: Tue Aug 27 15:01:02 2024 +0800 Partial: Just the testsuite bits. Vect: Reconcile the const_int operand type of unsigned .SAT_ADD The .SAT_AD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64

https://gcc.gnu.org/g:ef3f7e6aa699380b9925dabe7a1052a965622726 commit ef3f7e6aa699380b9925dabe7a1052a965622726 Author: Pan Li Date: Fri Aug 30 14:07:12 2024 +0800 RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64 In previous, we have some specially handling

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Test: Move pr116278 run test to dg/torture [NFC]

https://gcc.gnu.org/g:e9a4727900785a5a0a5fd0bf0df999ee69e3d6c9 commit e9a4727900785a5a0a5fd0bf0df999ee69e3d6c9 Author: Pan Li Date: Mon Aug 19 10:02:46 2024 +0800 Test: Move pr116278 run test to dg/torture [NFC] Move the run test of pr116278 to dg/torture and leave the risc-v the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM

https://gcc.gnu.org/g:246b7bd9a16863ac8abb5fb55240eefbf1026006 commit 246b7bd9a16863ac8abb5fb55240eefbf1026006 Author: Pan Li Date: Fri Aug 30 08:36:45 2024 +0800 RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM This patch would like to add test cases for the unsig

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 4 of unsigned vector .SAT_ADD IMM

https://gcc.gnu.org/g:b2887fd8a312b02e23d5e6ae0191f517e4c421a3 commit b2887fd8a312b02e23d5e6ae0191f517e4c421a3 Author: Pan Li Date: Fri Aug 30 11:01:37 2024 +0800 RISC-V: Add testcases for form 4 of unsigned vector .SAT_ADD IMM This patch would like to add test cases for the unsig

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix subreg of VLS modes larger than a vector [PR116086].

https://gcc.gnu.org/g:edba00e457e7677ffe66292090d60f8d50d70ee7 commit edba00e457e7677ffe66292090d60f8d50d70ee7 Author: Robin Dapp Date: Tue Aug 27 10:25:34 2024 +0200 RISC-V: Fix subreg of VLS modes larger than a vector [PR116086]. When the source mode is potentially larger than o

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2

https://gcc.gnu.org/g:94f4b718c181c9fe1f27a53c8babd38fa46c1640 commit 94f4b718c181c9fe1f27a53c8babd38fa46c1640 Author: Pan Li Date: Sun Aug 18 12:49:47 2024 +0800 RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2 This patch would like to add test cases for t

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3

https://gcc.gnu.org/g:d4f551d4316a38ea8ad9a1fe740dca5d4cbbd77c commit d4f551d4316a38ea8ad9a1fe740dca5d4cbbd77c Author: Pan Li Date: Sun Aug 18 14:08:21 2024 +0800 RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3 This patch would like to add test cases for t

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed][PR rtl-optimization/116544] Fix test for promoted subregs

https://gcc.gnu.org/g:f35d49f0eb8ffc614cf233ad05b2fe86791c6719 commit f35d49f0eb8ffc614cf233ad05b2fe86791c6719 Author: Jeff Law Date: Sun Sep 1 22:16:04 2024 -0600 [committed][PR rtl-optimization/116544] Fix test for promoted subregs This is a small bug in the ext-dce code's handl

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32.

https://gcc.gnu.org/g:82d58b78291d4108435da4411e8ebfa840ee4dc9 commit 82d58b78291d4108435da4411e8ebfa840ee4dc9 Author: Xianmiao Qu Date: Sun Sep 1 22:28:13 2024 -0600 [PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32. Currently, in RV32, even with the D extens

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Support form 1 of integer scalar .SAT_ADD

https://gcc.gnu.org/g:cb75d2d9eca78adc5a95884bdd19907c330ab5aa commit cb75d2d9eca78adc5a95884bdd19907c330ab5aa Author: Pan Li Date: Thu Aug 29 11:25:44 2024 +0800 RISC-V: Support form 1 of integer scalar .SAT_ADD This patch would like to support the scalar signed ssadd pattern

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR target/115921] Improve reassociation for rv64

https://gcc.gnu.org/g:0ff3a68e122baeafff5d58bad57ad0052dede067 commit 0ff3a68e122baeafff5d58bad57ad0052dede067 Author: Jeff Law Date: Tue Sep 3 06:45:30 2024 -0600 [PR target/115921] Improve reassociation for rv64 As Jovan pointed out in pr115921, we're not reassociating expressio

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Drop file that should not have been committed.

https://gcc.gnu.org/g:98d6e0eefeaa53d6482ca1968d95a22455996af3 commit 98d6e0eefeaa53d6482ca1968d95a22455996af3 Author: Jeff Law Date: Tue Sep 3 09:30:35 2024 -0600 Drop file that should not have been committed. * J: Drop file that should not have been committed (c

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD

https://gcc.gnu.org/g:b856428ef3b05b8fd69b439ade1b0cb1bb6e185e commit b856428ef3b05b8fd69b439ade1b0cb1bb6e185e Author: Pan Li Date: Mon Sep 2 15:54:43 2024 +0800 RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD This patch would like to allow the IMM operand of the unsigned

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 1/3] RISC-V: Improve codegen for negative repeating large constants

https://gcc.gnu.org/g:2d69f0e3a2e86b3d637cf2440d12ced120db31b7 commit 2d69f0e3a2e86b3d637cf2440d12ced120db31b7 Author: Raphael Moreira Zinsly Date: Wed Sep 4 17:21:24 2024 -0600 [PATCH 1/3] RISC-V: Improve codegen for negative repeating large constants Improve handling of constant

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Fix scan test output after recent path-splitting changes

https://gcc.gnu.org/g:80ad2d7bf8d40f8fb384855b06b8c97ed5371015 commit 80ad2d7bf8d40f8fb384855b06b8c97ed5371015 Author: Jeff Law Date: Wed Sep 4 12:07:09 2024 -0600 [RISC-V] Fix scan test output after recent path-splitting changes The recent path splitting changes from Andrew resul

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Fix sign/carry bit handling in ext-dce.

https://gcc.gnu.org/g:8754b967c81742fa33f65a75ed87834feeff95b9 commit 8754b967c81742fa33f65a75ed87834feeff95b9 Author: Jeff Law Date: Mon Jul 15 16:57:44 2024 -0600 Fix sign/carry bit handling in ext-dce. My change to fix a ubsan issue broke handling propagation of the carry/sign

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Just the testsuite changes...

https://gcc.gnu.org/g:5c27d6ce4cc63259d12e77eeda671adbc0d11530 commit 5c27d6ce4cc63259d12e77eeda671adbc0d11530 Author: Pan Li Date: Sat Aug 24 10:16:28 2024 +0800 Just the testsuite changes... Match: Add int type fits check for .SAT_ADD imm operand This patch would like t

[gcc r15-3461] i386: Integrate BFmode for Enhanced Vectorization in ix86_preferred_simd_mode

https://gcc.gnu.org/g:b851bce473d8e573b1b586c71d47e71067b4fa66 commit r15-3461-gb851bce473d8e573b1b586c71d47e71067b4fa66 Author: Levy Hsu Date: Tue Sep 3 15:44:06 2024 +0930 i386: Integrate BFmode for Enhanced Vectorization in ix86_preferred_simd_mode This change adds BFmode supp

[gcc r15-3462] i386: Support partial signbit/xorsign/copysign/abs/neg/and/xor/ior/andn for V2BF/V4BF

https://gcc.gnu.org/g:d0c86be1ce7131aeca2cf3304a8d65a00da4f12a commit r15-3462-gd0c86be1ce7131aeca2cf3304a8d65a00da4f12a Author: Levy Hsu Date: Mon Sep 2 13:27:46 2024 +0930 i386: Support partial signbit/xorsign/copysign/abs/neg/and/xor/ior/andn for V2BF/V4BF This patch adds supp

[gcc r15-3464] i386: Support partial vectorized FMA for V2BF/V4BF

https://gcc.gnu.org/g:f9ca3fd1fe30f3ee6725bfe4a612e9a1234c11ac commit r15-3464-gf9ca3fd1fe30f3ee6725bfe4a612e9a1234c11ac Author: Levy Hsu Date: Mon Sep 2 13:52:38 2024 +0800 i386: Support partial vectorized FMA for V2BF/V4BF This patch introduces support for vectorized FMA operati

[gcc(refs/users/meissner/heads/work177-vpair)] Initial vector-pair.h support

https://gcc.gnu.org/g:4362442ef3a8738a62ba36dfab2829705de71044 commit 4362442ef3a8738a62ba36dfab2829705de71044 Author: Michael Meissner Date: Wed Sep 4 22:18:39 2024 -0400 Initial vector-pair.h support 2024-09-03 Michael Meissner gcc/ * config.gcc (pow

[gcc(refs/users/meissner/heads/work177-vpair)] Add support for vector pair unary and binary operations.

https://gcc.gnu.org/g:ffd0ad5a0e7fe838b9137ebf7094e6cb8510c991 commit ffd0ad5a0e7fe838b9137ebf7094e6cb8510c991 Author: Michael Meissner Date: Wed Sep 4 22:45:52 2024 -0400 Add support for vector pair unary and binary operations. 2024-09-04 Michael Meissner gcc/

[gcc(refs/users/meissner/heads/work177-vpair)] Add vector pair init and splat.

https://gcc.gnu.org/g:7f65d3e030ef489b057c8a8409a3aefc7cd62ede commit 7f65d3e030ef489b057c8a8409a3aefc7cd62ede Author: Michael Meissner Date: Wed Sep 4 23:12:07 2024 -0400 Add vector pair init and splat. 2024-09-04 Michael Meissner gcc/ * config/rs6000

[gcc(refs/users/meissner/heads/work177-vpair)] Add support for vector pair fma operations.

https://gcc.gnu.org/g:bbb392f70a0774dc47e3cf31a8d4c74e3e7572e8 commit bbb392f70a0774dc47e3cf31a8d4c74e3e7572e8 Author: Michael Meissner Date: Wed Sep 4 22:55:54 2024 -0400 Add support for vector pair fma operations. 2024-09-04 Michael Meissner gcc/ * c

[gcc(refs/users/meissner/heads/work177-vpair)] Add vector pair optimizations.

https://gcc.gnu.org/g:4913a857cdd00d6896b06a99b10ad7961681946a commit 4913a857cdd00d6896b06a99b10ad7961681946a Author: Michael Meissner Date: Wed Sep 4 23:24:51 2024 -0400 Add vector pair optimizations. 2024-09-04 Michael Meissner gcc/ * config/rs6000/

[gcc(refs/users/meissner/heads/work177-vpair)] Update ChangeLog.*

https://gcc.gnu.org/g:f78233d1130358c2faf0c2c8f9a7f0818a548bd7 commit f78233d1130358c2faf0c2c8f9a7f0818a548bd7 Author: Michael Meissner Date: Wed Sep 4 23:28:28 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.vpair | 117 +++- 1 file

[gcc r15-3465] [PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection

https://gcc.gnu.org/g:de3ca363811a3974e4398ecdb1db2274efd61a1c commit r15-3465-gde3ca363811a3974e4398ecdb1db2274efd61a1c Author: Palmer Dabbelt Date: Wed Sep 4 21:34:31 2024 -0600 [PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection These tests were checking th

[gcc r15-3466] Handle 'NUM' in 'PUSH_INSERT_PASSES_WITHIN'

https://gcc.gnu.org/g:22af50a48d2b4371ee6d805d95f56212fbe611b1 commit r15-3466-g22af50a48d2b4371ee6d805d95f56212fbe611b1 Author: Thomas Schwinge Date: Fri Jun 28 12:10:12 2024 +0200 Handle 'NUM' in 'PUSH_INSERT_PASSES_WITHIN' ..., such that also for repeated 'NEXT_PASS', 'PUSH_INS