https://gcc.gnu.org/g:b2887fd8a312b02e23d5e6ae0191f517e4c421a3
commit b2887fd8a312b02e23d5e6ae0191f517e4c421a3
Author: Pan Li <pan2...@intel.com>
Date: Fri Aug 30 11:01:37 2024 +0800
RISC-V: Add testcases for form 4 of unsigned vector .SAT_ADD IMM
This patch would like to add test cases for the unsigned vector .SAT_ADD
when one of the operand is IMM.
Form 4:
#define DEF_VEC_SAT_U_ADD_IMM_FMT_4(T, IMM)
\
T __attribute__((noinline))
\
vec_sat_u_add_imm##IMM##_##T##_fmt_4 (T *out, T *in, unsigned limit)
\
{
\
unsigned i;
\
T ret;
\
for (i = 0; i < limit; i++)
\
{
\
out[i] = __builtin_add_overflow (in[i], IMM, &ret) == 0 ? ret : -1;
\
}
\
}
DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint64_t, 123)
The below test are passed for this patch.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper
macros.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-13.c:
New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-14.c:
New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-15.c:
New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-16.c:
New test.
Signed-off-by: Pan Li <pan2...@intel.com>
(cherry picked from commit 56ed1dfa79c436b769f3266258d34d160b4330d9)
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c | 14 +++++++++++
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c | 14 +++++++++++
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c | 14 +++++++++++
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c | 14 +++++++++++
.../rvv/autovec/binop/vec_sat_u_add_imm-run-13.c | 28 ++++++++++++++++++++++
.../rvv/autovec/binop/vec_sat_u_add_imm-run-14.c | 28 ++++++++++++++++++++++
.../rvv/autovec/binop/vec_sat_u_add_imm-run-15.c | 28 ++++++++++++++++++++++
.../rvv/autovec/binop/vec_sat_u_add_imm-run-16.c | 28 ++++++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/vec_sat_arith.h | 20 ++++++++++++++++
9 files changed, 188 insertions(+)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c
new file mode 100644
index 00000000000..a9439dff39f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_add_imm9u_uint8_t_fmt_4:
+** ...
+** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*9
+** ...
+*/
+DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint8_t, 9u)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c
new file mode 100644
index 00000000000..dbe47497599
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_add_imm15_uint16_t_fmt_4:
+** ...
+** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*15
+** ...
+*/
+DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint16_t, 15)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c
new file mode 100644
index 00000000000..0ac2e1b2942
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_add_imm33u_uint32_t_fmt_4:
+** ...
+** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** ...
+*/
+DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint32_t, 33u)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c
new file mode 100644
index 00000000000..9574966401a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_add_imm129ull_uint64_t_fmt_4:
+** ...
+** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** ...
+*/
+DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint64_t, 129ull)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-13.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-13.c
new file mode 100644
index 00000000000..612638c7276
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-13.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint8_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 0u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 1u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 254u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 255u)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm);
+
+ RUN (T, out, d[0][0], d[0][1], 0u, N);
+ RUN (T, out, d[1][0], d[1][1], 1u, N);
+ RUN (T, out, d[2][0], d[2][1], 254u, N);
+ RUN (T, out, d[3][0], d[3][1], 255u, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-14.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-14.c
new file mode 100644
index 00000000000..c5fb4d16b52
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-14.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint16_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 0u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 1u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 65534u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 65535u)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm);
+
+ RUN (T, out, d[0][0], d[0][1], 0u, N);
+ RUN (T, out, d[1][0], d[1][1], 1u, N);
+ RUN (T, out, d[2][0], d[2][1], 65534u, N);
+ RUN (T, out, d[3][0], d[3][1], 65535u, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-15.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-15.c
new file mode 100644
index 00000000000..e45beef7c38
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-15.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint32_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 0u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 1u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 4294967295u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 4294967294u)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm);
+
+ RUN (T, out, d[0][0], d[0][1], 0u, N);
+ RUN (T, out, d[1][0], d[1][1], 1u, N);
+ RUN (T, out, d[2][0], d[2][1], 4294967294u, N);
+ RUN (T, out, d[3][0], d[3][1], 4294967295u, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-16.c
new file mode 100644
index 00000000000..f0a82f31d4f
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-16.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint64_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 0ull)
+DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 1ull)
+DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 18446744073709551614ull)
+DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 18446744073709551615ull)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm);
+
+ RUN (T, out, d[0][0], d[0][1], 0ull, N);
+ RUN (T, out, d[1][0], d[1][1], 1ull, N);
+ RUN (T, out, d[2][0], d[2][1], 18446744073709551614ull, N);
+ RUN (T, out, d[3][0], d[3][1], 18446744073709551615ull, N);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
index deb6bb82eba..23edc48d5bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
@@ -183,6 +183,20 @@ vec_sat_u_add_imm##IMM##_##T##_fmt_3 (T *out, T *in,
unsigned limit) \
#define DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP(T, IMM) \
DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM)
+#define DEF_VEC_SAT_U_ADD_IMM_FMT_4(T, IMM) \
+T __attribute__((noinline)) \
+vec_sat_u_add_imm##IMM##_##T##_fmt_4 (T *out, T *in, unsigned limit) \
+{ \
+ unsigned i; \
+ T ret; \
+ for (i = 0; i < limit; i++) \
+ { \
+ out[i] = __builtin_add_overflow (in[i], IMM, &ret) == 0 ? ret : -1; \
+ } \
+}
+#define DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP(T, IMM) \
+ DEF_VEC_SAT_U_ADD_IMM_FMT_4(T, IMM)
+
#define RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N) \
vec_sat_u_add_imm##IMM##_##T##_fmt_1(out, op_1, N); \
VALIDATE_RESULT (out, expect, N)
@@ -201,6 +215,12 @@ vec_sat_u_add_imm##IMM##_##T##_fmt_3 (T *out, T *in,
unsigned limit) \
#define RUN_VEC_SAT_U_ADD_IMM_FMT_3_WRAP(T, out, op_1, expect, IMM, N) \
RUN_VEC_SAT_U_ADD_IMM_FMT_3(T, out, op_1, expect, IMM, N)
+#define RUN_VEC_SAT_U_ADD_IMM_FMT_4(T, out, op_1, expect, IMM, N) \
+ vec_sat_u_add_imm##IMM##_##T##_fmt_4(out, op_1, N); \
+ VALIDATE_RESULT (out, expect, N)
+#define RUN_VEC_SAT_U_ADD_IMM_FMT_4_WRAP(T, out, op_1, expect, IMM, N) \
+ RUN_VEC_SAT_U_ADD_IMM_FMT_4(T, out, op_1, expect, IMM, N)
+
/******************************************************************************/
/* Saturation Sub (Unsigned and Signed)
*/
/******************************************************************************/
