[gcc r16-2789] i386: Extend recognition of high-reg rvalues [PR121306]

https://gcc.gnu.org/g:5305f84c3be3de9397907dfaf151477579d91c77 commit r16-2789-g5305f84c3be3de9397907dfaf151477579d91c77 Author: Richard Sandiford Date: Tue Aug 5 14:42:34 2025 +0100 i386: Extend recognition of high-reg rvalues [PR121306] The i386 high-register patterns used thing

[gcc r16-2740] aarch64: Use VNx16BI for svac*

https://gcc.gnu.org/g:6e26bf69004d5e5476d8813f0546bbb6034aead9 commit r16-2740-g6e26bf69004d5e5476d8813f0546bbb6034aead9 Author: Richard Sandiford Date: Mon Aug 4 11:45:33 2025 +0100 aarch64: Use VNx16BI for svac* This patch continues the work of making ACLE intrinsics use VNx16BI

[gcc r16-2738] aarch64: Use VNx16BI for svcmp*_wide

https://gcc.gnu.org/g:690586e7960a9fb0b9939a770a37b6c9bf74a8bf commit r16-2738-g690586e7960a9fb0b9939a770a37b6c9bf74a8bf Author: Richard Sandiford Date: Mon Aug 4 11:45:32 2025 +0100 aarch64: Use VNx16BI for svcmp*_wide This patch continues the work of making ACLE intrinsics use V

[gcc r16-2745] aarch64: Check the mode of SVE ACLE function results

https://gcc.gnu.org/g:d9f34c951ab1f5ba67f3a1c95e2533cff6230b85 commit r16-2745-gd9f34c951ab1f5ba67f3a1c95e2533cff6230b85 Author: Richard Sandiford Date: Mon Aug 4 11:45:36 2025 +0100 aarch64: Check the mode of SVE ACLE function results After previous patches, we should always get

[gcc r16-2743] aarch64: Use VNx16BI for svdup_b*

https://gcc.gnu.org/g:b768e2786f8c85097442bd52010fee1b7ed12ed2 commit r16-2743-gb768e2786f8c85097442bd52010fee1b7ed12ed2 Author: Richard Sandiford Date: Mon Aug 4 11:45:35 2025 +0100 aarch64: Use VNx16BI for svdup_b* This patch continues the work of making ACLE intrinsics use VNx1

[gcc r16-2744] aarch64: Use VNx16BI for svdupq_b*

https://gcc.gnu.org/g:f4915d9b6632ed0ea7e43027a9d5124bd067df49 commit r16-2744-gf4915d9b6632ed0ea7e43027a9d5124bd067df49 Author: Richard Sandiford Date: Mon Aug 4 11:45:36 2025 +0100 aarch64: Use VNx16BI for svdupq_b* This patch continues the work of making ACLE intrinsics use VNx

[gcc r16-2742] aarch64: Use VNx16BI for svpnext*

https://gcc.gnu.org/g:4ff15c5a998354c58dca19fc825c44dcb6d57bb6 commit r16-2742-g4ff15c5a998354c58dca19fc825c44dcb6d57bb6 Author: Richard Sandiford Date: Mon Aug 4 11:45:34 2025 +0100 aarch64: Use VNx16BI for svpnext* This patch continues the work of making ACLE intrinsics use VNx1

[gcc r16-2741] aarch64: Use VNx16BI for sv(n)match*

https://gcc.gnu.org/g:28a4dfe807afb292ef726a82d40c351743c3e345 commit r16-2741-g28a4dfe807afb292ef726a82d40c351743c3e345 Author: Richard Sandiford Date: Mon Aug 4 11:45:34 2025 +0100 aarch64: Use VNx16BI for sv(n)match* This patch continues the work of making ACLE intrinsics use V

[gcc r16-2737] aarch64: Drop unnecessary GPs in svcmp_wide PTEST patterns

https://gcc.gnu.org/g:dec30d6f9bf5600d221a73926d0c00bf12a5b6f5 commit r16-2737-gdec30d6f9bf5600d221a73926d0c00bf12a5b6f5 Author: Richard Sandiford Date: Mon Aug 4 11:45:32 2025 +0100 aarch64: Drop unnecessary GPs in svcmp_wide PTEST patterns Patterns that fuse a predicate operatio

[gcc r16-2736] aarch64: Use the correct GP mode in the svcmp_wide patterns

https://gcc.gnu.org/g:5e6ccffab91186878d7b7195fb356ba779417e36 commit r16-2736-g5e6ccffab91186878d7b7195fb356ba779417e36 Author: Richard Sandiford Date: Mon Aug 4 11:45:31 2025 +0100 aarch64: Use the correct GP mode in the svcmp_wide patterns The patterns for the svcmp_wide intrin

[gcc r16-2733] aarch64: Use VNx16BI for svrev_b* [PR121294]

https://gcc.gnu.org/g:dcb02ff8229882cbfb04155643054c1535244d7b commit r16-2733-gdcb02ff8229882cbfb04155643054c1535244d7b Author: Richard Sandiford Date: Mon Aug 4 11:45:29 2025 +0100 aarch64: Use VNx16BI for svrev_b* [PR121294] The previous patch for PR121294 handled svtrn1/2, svu

[gcc r16-2739] aarch64: Use VNx16BI for floating-point svcmp*

https://gcc.gnu.org/g:2cf2cc8183e70d00744a22f07092d24519bb91c5 commit r16-2739-g2cf2cc8183e70d00744a22f07092d24519bb91c5 Author: Richard Sandiford Date: Mon Aug 4 11:45:33 2025 +0100 aarch64: Use VNx16BI for floating-point svcmp* This patch continues the work of making ACLE intrin

[gcc r16-2735] aarch64: Use VNx16BI for non-widening integer svcmp*

https://gcc.gnu.org/g:c17b47b9c0a3bbd39723596a647bd9a856fc445f commit r16-2735-gc17b47b9c0a3bbd39723596a647bd9a856fc445f Author: Richard Sandiford Date: Mon Aug 4 11:45:31 2025 +0100 aarch64: Use VNx16BI for non-widening integer svcmp* This patch continues the work of making ACLE

[gcc r16-2734] aarch64: Use VNx16BI for svunpklo/hi_b

https://gcc.gnu.org/g:2b419b709123194d3124a57c57556b0185fd2684 commit r16-2734-g2b419b709123194d3124a57c57556b0185fd2684 Author: Richard Sandiford Date: Mon Aug 4 11:45:30 2025 +0100 aarch64: Use VNx16BI for svunpklo/hi_b This patch continues the work of making ACLE intrinsics use

[gcc r16-2730] aarch64: Improve svdupq_lane expension for big-endian [PR121293]

https://gcc.gnu.org/g:fcfbe83d88c1bfae49e654b5095ebe46cbe361d8 commit r16-2730-gfcfbe83d88c1bfae49e654b5095ebe46cbe361d8 Author: Richard Sandiford Date: Mon Aug 4 11:45:28 2025 +0100 aarch64: Improve svdupq_lane expension for big-endian [PR121293] If the index to svdupq_lane is va

[gcc r16-2732] aarch64: Use VNx16BI for more permutations [PR121294]

https://gcc.gnu.org/g:13c8c9d8d11490698a877d604c029170fcb7fdff commit r16-2732-g13c8c9d8d11490698a877d604c029170fcb7fdff Author: Richard Sandiford Date: Mon Aug 4 11:45:29 2025 +0100 aarch64: Use VNx16BI for more permutations [PR121294] The patterns for the predicate forms of svtr

[gcc r16-2731] aarch64: Use VNx16BI for more SVE WHILE* results [PR121118]

https://gcc.gnu.org/g:f702b593e7268ab161053bafd097f1b09933b783 commit r16-2731-gf702b593e7268ab161053bafd097f1b09933b783 Author: Richard Sandiford Date: Mon Aug 4 11:45:28 2025 +0100 aarch64: Use VNx16BI for more SVE WHILE* results [PR121118] PR121118 is about a case where we try

[gcc r16-2614] simplify-rtx: Simplify subregs of logic ops

https://gcc.gnu.org/g:965564eafb721f813a3112f1bba8d8fae32b commit r16-2614-g965564eafb721f813a3112f1bba8d8fae32b Author: Richard Sandiford Date: Tue Jul 29 15:58:34 2025 +0100 simplify-rtx: Simplify subregs of logic ops This patch adds a new rule for distributing lowpart s

[gcc r16-2613] testsuite: Generalise aarch64/saturating_arithmetic*.c

https://gcc.gnu.org/g:cc9c041fd1c84de8960bb2f3b30f8d53b059cba4 commit r16-2613-gcc9c041fd1c84de8960bb2f3b30f8d53b059cba4 Author: Richard Sandiford Date: Tue Jul 29 15:58:33 2025 +0100 testsuite: Generalise aarch64/saturating_arithmetic*.c gcc.target/aarch64/saturating_arithmetic_{

[gcc r16-2612] testsuite: Make aarch64/cmpbr.c more forgiving

https://gcc.gnu.org/g:9c3f2cb35d03a33a49f996855e913be6d3af2437 commit r16-2612-g9c3f2cb35d03a33a49f996855e913be6d3af2437 Author: Richard Sandiford Date: Tue Jul 29 15:58:33 2025 +0100 testsuite: Make aarch64/cmpbr.c more forgiving The 8-bit and 16-bit tests in cmpbr.c assumed an i

[gcc r16-2611] aarch64: Fix function_expander::get_reg_target

https://gcc.gnu.org/g:668936caf0662a4eea62144c98fdfc8cf30b79d8 commit r16-2611-g668936caf0662a4eea62144c98fdfc8cf30b79d8 Author: Richard Sandiford Date: Tue Jul 29 15:58:32 2025 +0100 aarch64: Fix function_expander::get_reg_target function_expander::get_reg_target didn't actually

[gcc r14-11910] aarch64: Fix neon-sve-bridge.c failures for big-endian

https://gcc.gnu.org/g:82f5dd231e2e25bc18853f3f1d217a6bde778b20 commit r14-11910-g82f5dd231e2e25bc18853f3f1d217a6bde778b20 Author: Richard Sandiford Date: Sat Jul 26 18:38:47 2025 +0100 aarch64: Fix neon-sve-bridge.c failures for big-endian Lowpart subregs are generally disallowed

[gcc r14-11913] aarch64: Tweak handling of general SVE permutes [PR121027]

https://gcc.gnu.org/g:43f59fcd1e33fc98adc5ff70ac82cc16f77b9ab4 commit r14-11913-g43f59fcd1e33fc98adc5ff70ac82cc16f77b9ab4 Author: Richard Sandiford Date: Sat Jul 26 18:38:49 2025 +0100 aarch64: Tweak handling of general SVE permutes [PR121027] This PR is partly about a code qualit

[gcc r14-11912] aarch64: Fix general permutes of svbfloat16_ts [PR121027]

https://gcc.gnu.org/g:86ecf3e5832a3fd1fc0ecfbb03e91ca8e6aa806e commit r14-11912-g86ecf3e5832a3fd1fc0ecfbb03e91ca8e6aa806e Author: Richard Sandiford Date: Sat Jul 26 18:38:48 2025 +0100 aarch64: Fix general permutes of svbfloat16_ts [PR121027] Testing gcc.target/aarch64/sve/permute

[gcc r14-11911] aarch64: Fix ZIP1 order in aarch64_expand_vector_init [PR118891]

https://gcc.gnu.org/g:7ff0631724d3332b21dc0b0adef93adc8c8cfff2 commit r14-11911-g7ff0631724d3332b21dc0b0adef93adc8c8cfff2 Author: Richard Sandiford Date: Sat Jul 26 18:38:48 2025 +0100 aarch64: Fix ZIP1 order in aarch64_expand_vector_init [PR118891] aarch64_expand_vector_init cont

[gcc r14-11909] vect: Fix VEC_WIDEN_PLUS_HI/LO choice for big-endian [PR118891]

https://gcc.gnu.org/g:d755d8107d336ca1a5805370fb6c5fb4df2c5da4 commit r14-11909-gd755d8107d336ca1a5805370fb6c5fb4df2c5da4 Author: Richard Sandiford Date: Sat Jul 26 18:38:46 2025 +0100 vect: Fix VEC_WIDEN_PLUS_HI/LO choice for big-endian [PR118891] In the tree codes and optabs, th

[gcc r15-10027] aarch64: Tweak handling of general SVE permutes [PR121027]

https://gcc.gnu.org/g:b8be49c928c9f81f1faa39d462880fc47a2b7d0c commit r15-10027-gb8be49c928c9f81f1faa39d462880fc47a2b7d0c Author: Richard Sandiford Date: Mon Jul 21 15:41:05 2025 +0100 aarch64: Tweak handling of general SVE permutes [PR121027] This PR is partly about a code qualit

[gcc r15-10026] aarch64: Fix LD1Q and ST1Q failures for big-endian

https://gcc.gnu.org/g:a413f83cad6b0afdbbe26b9481e552abec3f5415 commit r15-10026-ga413f83cad6b0afdbbe26b9481e552abec3f5415 Author: Richard Sandiford Date: Mon Jul 21 15:41:05 2025 +0100 aarch64: Fix LD1Q and ST1Q failures for big-endian LD1Q gathers and ST1Q scatters are unusual in

[gcc r15-10024] aarch64: Extend HVLA permutations to big-endian

https://gcc.gnu.org/g:24a6fe0effd973f077c7576315a0578c01288a38 commit r15-10024-g24a6fe0effd973f077c7576315a0578c01288a38 Author: Richard Sandiford Date: Mon Jul 21 15:41:04 2025 +0100 aarch64: Extend HVLA permutations to big-endian TARGET_VECTORIZE_VEC_PERM_CONST has code to matc

[gcc r15-10025] testsuite: Add -funwind-tables to sve*/pfalse* tests

https://gcc.gnu.org/g:79a9996e162194e981ea0d058a134ebddafc30cf commit r15-10025-g79a9996e162194e981ea0d058a134ebddafc30cf Author: Richard Sandiford Date: Mon Jul 21 15:41:04 2025 +0100 testsuite: Add -funwind-tables to sve*/pfalse* tests The SVE svpfalse folding tests use CFI dire

[gcc r15-10021] Make the RTL frontend set REG_NREGS correctly

https://gcc.gnu.org/g:abacc79405dfd8a5148f5a79397574ebae74c2d3 commit r15-10021-gabacc79405dfd8a5148f5a79397574ebae74c2d3 Author: Richard Sandiford Date: Mon Jul 21 15:41:02 2025 +0100 Make the RTL frontend set REG_NREGS correctly While working on a new testcase that uses the RTL

[gcc r15-10022] aarch64: Some fixes for SVE INDEX constants

https://gcc.gnu.org/g:c2371624f436e078d507ed6877d40812cb2b703f commit r15-10022-gc2371624f436e078d507ed6877d40812cb2b703f Author: Richard Sandiford Date: Mon Jul 21 15:41:02 2025 +0100 aarch64: Some fixes for SVE INDEX constants When using SVE INDEX to load an Advanced SIMD vector

[gcc r15-10023] aarch64: Fix endianness of DFmode vector constants

https://gcc.gnu.org/g:526efb6bfc148e1ca5d1ec7dd101cb18fdca5302 commit r15-10023-g526efb6bfc148e1ca5d1ec7dd101cb18fdca5302 Author: Richard Sandiford Date: Mon Jul 21 15:41:03 2025 +0100 aarch64: Fix endianness of DFmode vector constants aarch64_simd_valid_imm tries to decompose a c

[gcc r15-10020] ext-dce: Fix subreg_lsb is_constant assumption (2)

https://gcc.gnu.org/g:0b6038c17cabdbc8b9bfd0d13e2dd6f74db78734 commit r15-10020-g0b6038c17cabdbc8b9bfd0d13e2dd6f74db78734 Author: Richard Sandiford Date: Mon Jul 21 15:41:01 2025 +0100 ext-dce: Fix subreg_lsb is_constant assumption (2) This patch fixes another instance of the prob

[gcc r15-10018] aarch64: Fix neon-sve-bridge.c failures for big-endian

https://gcc.gnu.org/g:eca9778fc8cabd032bbb68de3765aa45dabbc3e4 commit r15-10018-geca9778fc8cabd032bbb68de3765aa45dabbc3e4 Author: Richard Sandiford Date: Mon Jul 21 15:41:00 2025 +0100 aarch64: Fix neon-sve-bridge.c failures for big-endian Lowpart subregs are generally disallowed

[gcc r15-10019] aarch64: Fix ZIP1 order in aarch64_expand_vector_init [PR118891]

https://gcc.gnu.org/g:d88c1b70a51513d11da7aca71a5d19363b5342a2 commit r15-10019-gd88c1b70a51513d11da7aca71a5d19363b5342a2 Author: Richard Sandiford Date: Mon Jul 21 15:41:01 2025 +0100 aarch64: Fix ZIP1 order in aarch64_expand_vector_init [PR118891] aarch64_expand_vector_init cont

[gcc r15-10017] ext-dce: Fix subreg_lsb is_constant assumption

https://gcc.gnu.org/g:9e8af6864b9fdfae109248a4d162bba9cc008b60 commit r15-10017-g9e8af6864b9fdfae109248a4d162bba9cc008b60 Author: Richard Sandiford Date: Mon Jul 21 15:41:00 2025 +0100 ext-dce: Fix subreg_lsb is_constant assumption ext-dce had: if (SUBREG_P (dst

[gcc r15-10016] vect: Fix VEC_WIDEN_PLUS_HI/LO choice for big-endian [PR118891]

https://gcc.gnu.org/g:2363ea8392b603bb5fd196a220a76a510e1115f5 commit r15-10016-g2363ea8392b603bb5fd196a220a76a510e1115f5 Author: Richard Sandiford Date: Mon Jul 21 15:40:59 2025 +0100 vect: Fix VEC_WIDEN_PLUS_HI/LO choice for big-endian [PR118891] In the tree codes and optabs, th

[gcc r16-2205] aarch64: Tweak handling of general SVE permutes [PR121027]

https://gcc.gnu.org/g:1f52396c6fc940224e9d858d49e41310a6dfa43d commit r16-2205-g1f52396c6fc940224e9d858d49e41310a6dfa43d Author: Richard Sandiford Date: Fri Jul 11 16:48:41 2025 +0100 aarch64: Tweak handling of general SVE permutes [PR121027] This PR is partly about a code quality

[gcc r16-2182] aarch64: Guard VF-based costing with !m_costing_for_scalar

https://gcc.gnu.org/g:a1e616955e9971fda54a160a49e6cf70dd838a0c commit r16-2182-ga1e616955e9971fda54a160a49e6cf70dd838a0c Author: Richard Sandiford Date: Thu Jul 10 22:00:41 2025 +0100 aarch64: Guard VF-based costing with !m_costing_for_scalar g:4b47acfe2b626d1276e229a0cf165e934813

[gcc r16-2178] aarch64: Fix LD1Q and ST1Q failures for big-endian

https://gcc.gnu.org/g:e7f049471c6caf22c65ac48773d864fca7a4cdc4 commit r16-2178-ge7f049471c6caf22c65ac48773d864fca7a4cdc4 Author: Richard Sandiford Date: Thu Jul 10 16:54:45 2025 +0100 aarch64: Fix LD1Q and ST1Q failures for big-endian LD1Q gathers and ST1Q scatters are unusual in

[gcc r16-2171] testsuite: Add -funwind-tables to sve*/pfalse* tests

https://gcc.gnu.org/g:2ff8da46152cbade579700823cc7b1460ddd91b8 commit r16-2171-g2ff8da46152cbade579700823cc7b1460ddd91b8 Author: Richard Sandiford Date: Thu Jul 10 14:23:57 2025 +0100 testsuite: Add -funwind-tables to sve*/pfalse* tests The SVE svpfalse folding tests use CFI direc

[gcc r16-2164] aarch64: Extend HVLA permutations to big-endian

https://gcc.gnu.org/g:3b870131487d786a74f27a89d0415c8207770f14 commit r16-2164-g3b870131487d786a74f27a89d0415c8207770f14 Author: Richard Sandiford Date: Thu Jul 10 10:57:28 2025 +0100 aarch64: Extend HVLA permutations to big-endian TARGET_VECTORIZE_VEC_PERM_CONST has code to match

[gcc r16-2151] aarch64: Fix endianness of DFmode vector constants

https://gcc.gnu.org/g:82dd19890b6139c4bac2385068a68613920ae1a2 commit r16-2151-g82dd19890b6139c4bac2385068a68613920ae1a2 Author: Richard Sandiford Date: Wed Jul 9 17:44:20 2025 +0100 aarch64: Fix endianness of DFmode vector constants aarch64_simd_valid_imm tries to decompose a con

[gcc r16-2145] aarch64: Some fixes for SVE INDEX constants

https://gcc.gnu.org/g:41c446389446a357172883389e36fd10c882ce6d commit r16-2145-g41c446389446a357172883389e36fd10c882ce6d Author: Richard Sandiford Date: Wed Jul 9 16:39:20 2025 +0100 aarch64: Some fixes for SVE INDEX constants When using SVE INDEX to load an Advanced SIMD vector,

[gcc r16-2144] Make the RTL frontend set REG_NREGS correctly

https://gcc.gnu.org/g:76db38d811a63a603deedfe327d5e201fc820444 commit r16-2144-g76db38d811a63a603deedfe327d5e201fc820444 Author: Richard Sandiford Date: Wed Jul 9 16:39:20 2025 +0100 Make the RTL frontend set REG_NREGS correctly While working on a new testcase that uses the RTL fr

[gcc r16-2137] testsuite: Add a couple of fstack_protector guards

https://gcc.gnu.org/g:87ef2e154e1a7ae65d2dd86a667bafd5525401c4 commit r16-2137-g87ef2e154e1a7ae65d2dd86a667bafd5525401c4 Author: Richard Sandiford Date: Wed Jul 9 15:01:17 2025 +0100 testsuite: Add a couple of fstack_protector guards These tests required runtime support for -fstac

[gcc r16-2136] ext-dce: Fix subreg_lsb is_constant assumption (2)

https://gcc.gnu.org/g:bddc41e290113dd9160b01f2fdf925a1876c8ee0 commit r16-2136-gbddc41e290113dd9160b01f2fdf925a1876c8ee0 Author: Richard Sandiford Date: Wed Jul 9 14:59:34 2025 +0100 ext-dce: Fix subreg_lsb is_constant assumption (2) This patch fixes another instance of the proble

[gcc r16-2052] vect: Fix VEC_WIDEN_PLUS_HI/LO choice for big-endian [PR118891]

https://gcc.gnu.org/g:ec54a14239b12d03c600c14f3ce9710e65cd33f1 commit r16-2052-gec54a14239b12d03c600c14f3ce9710e65cd33f1 Author: Richard Sandiford Date: Mon Jul 7 09:10:38 2025 +0100 vect: Fix VEC_WIDEN_PLUS_HI/LO choice for big-endian [PR118891] In the tree codes and optabs, the

[gcc r16-2050] aarch64: Fix neon-sve-bridge.c failures for big-endian

https://gcc.gnu.org/g:69c839c7361430ec27d1f13f909531b872588f27 commit r16-2050-g69c839c7361430ec27d1f13f909531b872588f27 Author: Richard Sandiford Date: Mon Jul 7 09:10:37 2025 +0100 aarch64: Fix neon-sve-bridge.c failures for big-endian Lowpart subregs are generally disallowed on

[gcc r16-2051] ext-dce: Fix subreg_lsb is_constant assumption

https://gcc.gnu.org/g:bf3037e923e9f91d93ab64bdf73a37f64f659fb9 commit r16-2051-gbf3037e923e9f91d93ab64bdf73a37f64f659fb9 Author: Richard Sandiford Date: Mon Jul 7 09:10:38 2025 +0100 ext-dce: Fix subreg_lsb is_constant assumption ext-dce had: if (SUBREG_P (dst)

[gcc r16-2049] aarch64: Fix ZIP1 order in aarch64_expand_vector_init [PR118891]

https://gcc.gnu.org/g:cb2b5471516c3c469f65d927a2a30eb15357e429 commit r16-2049-gcb2b5471516c3c469f65d927a2a30eb15357e429 Author: Richard Sandiford Date: Mon Jul 7 09:10:37 2025 +0100 aarch64: Fix ZIP1 order in aarch64_expand_vector_init [PR118891] aarch64_expand_vector_init contai

[gcc r16-1981] AArch64: rules for CMPBR instructions

https://gcc.gnu.org/g:2e95ef6ca3e97b8d66110b3d0cdc144dec56fb3b commit r16-1981-g2e95ef6ca3e97b8d66110b3d0cdc144dec56fb3b Author: Karl Meakin Date: Thu Jul 3 12:48:33 2025 +0100 AArch64: rules for CMPBR instructions Add rules for lowering `cbranch4` to CBB/CBH/CB when CMPBR ext

[gcc r16-1982] AArch64: make rules for CBZ/TBZ higher priority

https://gcc.gnu.org/g:44b9769593ac8bb01f869e0505f447d9dfe8add5 commit r16-1982-g44b9769593ac8bb01f869e0505f447d9dfe8add5 Author: Karl Meakin Date: Thu Jul 3 12:48:34 2025 +0100 AArch64: make rules for CBZ/TBZ higher priority Move the rules for CBZ/TBZ to be above the rules for

[gcc r16-1980] AArch64: precommit test for CMPBR instructions

https://gcc.gnu.org/g:bda03ce9125af8910e77b407a701a76b93b5ba57 commit r16-1980-gbda03ce9125af8910e77b407a701a76b93b5ba57 Author: Karl Meakin Date: Thu Jul 3 12:48:32 2025 +0100 AArch64: precommit test for CMPBR instructions Commit the test file `cmpbr.c` before rules for generatin

[gcc r16-1978] AArch64: make `far_branch` attribute a boolean

https://gcc.gnu.org/g:6cc3cdddeb362b827b5d1f97a21291623cb1bd3a commit r16-1978-g6cc3cdddeb362b827b5d1f97a21291623cb1bd3a Author: Karl Meakin Date: Thu Jul 3 12:48:30 2025 +0100 AArch64: make `far_branch` attribute a boolean The `far_branch` attribute only ever takes the values 0 o

[gcc r16-1979] AArch64: recognize `+cmpbr` option

https://gcc.gnu.org/g:2e021e34ea18d88fde8ae3b7400828d054d6d4af commit r16-1979-g2e021e34ea18d88fde8ae3b7400828d054d6d4af Author: Karl Meakin Date: Thu Jul 3 12:48:31 2025 +0100 AArch64: recognize `+cmpbr` option Add the `+cmpbr` option to enable the FEAT_CMPBR architectural ex

[gcc r16-1977] AArch64: add constants for branch displacements

https://gcc.gnu.org/g:70905bad8ea7e9e5f807b54ad3fe183f643cdbf2 commit r16-1977-g70905bad8ea7e9e5f807b54ad3fe183f643cdbf2 Author: Karl Meakin Date: Thu Jul 3 12:48:29 2025 +0100 AArch64: add constants for branch displacements Extract the hardcoded values for the minimum PC-relative

[gcc r16-1975] AArch64: reformat branch instruction rules

https://gcc.gnu.org/g:cfb1a083e16507feb8bbb85903611aac3772aaef commit r16-1975-gcfb1a083e16507feb8bbb85903611aac3772aaef Author: Karl Meakin Date: Thu Jul 3 12:48:28 2025 +0100 AArch64: reformat branch instruction rules Make the formatting of the RTL templates in the rules for bra

[gcc r16-1976] AArch64: rename branch instruction rules

https://gcc.gnu.org/g:2cc9b03a84601b7951e5e0a24f5174387f564f27 commit r16-1976-g2cc9b03a84601b7951e5e0a24f5174387f564f27 Author: Karl Meakin Date: Thu Jul 3 12:48:28 2025 +0100 AArch64: rename branch instruction rules Give the `define_insn` rules used in lowering `cbranch4` to RTL

[gcc r16-1974] AArch64: place branch instruction rules together

https://gcc.gnu.org/g:53242a56844e484e8694dc073be607f16ebbd8d4 commit r16-1974-g53242a56844e484e8694dc073be607f16ebbd8d4 Author: Karl Meakin Date: Thu Jul 3 12:48:27 2025 +0100 AArch64: place branch instruction rules together The rules for conditional branches were spread througho

[gcc r14-11871] aarch64: Incorrect removal of ZA restore [PR120624]

https://gcc.gnu.org/g:72b828227f8faf8f0a85735a5c27545378cf20c5 commit r14-11871-g72b828227f8faf8f0a85735a5c27545378cf20c5 Author: Richard Sandiford Date: Thu Jul 3 08:12:42 2025 +0100 aarch64: Incorrect removal of ZA restore [PR120624] The PCS defines a lazy save scheme for managi

[gcc r16-1892] AArch64 SIMD: convert mvn+shrn into mvni+subhn

https://gcc.gnu.org/g:1cbb3122cb2779198b0dcfb8afc28df711e64138 commit r16-1892-g1cbb3122cb2779198b0dcfb8afc28df711e64138 Author: Remi Machet Date: Tue Jul 1 13:45:04 2025 +0100 AArch64 SIMD: convert mvn+shrn into mvni+subhn Add an optimization to aarch64 SIMD converting mvn+shrn i

[gcc r16-1827] ivopts: Fix scan-assembler-not regexes for aarch64/sve test

https://gcc.gnu.org/g:7a1aea7e6a80c742e7e434c9a8e3501d109e0fbf commit r16-1827-g7a1aea7e6a80c742e7e434c9a8e3501d109e0fbf Author: Christopher Bazley Date: Mon Jun 30 16:59:56 2025 +0100 ivopts: Fix scan-assembler-not regexes for aarch64/sve test The test added by r16-1671-ge7ff8e8d

[gcc r16-1774] lra: Check for null lowpart_subregs [PR120733]

https://gcc.gnu.org/g:da3f2a561649c7c4899449c6b3ab2b6d67792a71 commit r16-1774-gda3f2a561649c7c4899449c6b3ab2b6d67792a71 Author: Richard Sandiford Date: Mon Jun 30 08:52:26 2025 +0100 lra: Check for null lowpart_subregs [PR120733] lra-eliminations.cc:move_plus_up tries to:

[gcc r15-9860] aarch64: Incorrect removal of ZA restore [PR120624]

https://gcc.gnu.org/g:cb3c5b7d15cdb9373d102e7045c0823526a9c660 commit r15-9860-gcb3c5b7d15cdb9373d102e7045c0823526a9c660 Author: Richard Sandiford Date: Wed Jun 25 17:28:42 2025 +0100 aarch64: Incorrect removal of ZA restore [PR120624] The PCS defines a lazy save scheme for managi

[gcc r15-9859] rtl-ssa: Reject non-address uses of autoinc regs [PR120347]

https://gcc.gnu.org/g:2efe8cc55581a5fecb388646f1908eed4ec11a63 commit r15-9859-g2efe8cc55581a5fecb388646f1908eed4ec11a63 Author: Richard Sandiford Date: Wed Jun 25 17:28:42 2025 +0100 rtl-ssa: Reject non-address uses of autoinc regs [PR120347] As the rtl.texi documentation of RTX_

[gcc r16-1669] rtl-ssa: Rewrite process_uses_of_deleted_def [PR120745]

https://gcc.gnu.org/g:76f7f91de08de49f39c612bdc9a44a6a8b45325f commit r16-1669-g76f7f91de08de49f39c612bdc9a44a6a8b45325f Author: Richard Sandiford Date: Wed Jun 25 10:44:34 2025 +0100 rtl-ssa: Rewrite process_uses_of_deleted_def [PR120745] process_uses_of_deleted_def seems to have

[gcc r16-1621] vregs: Use force_subreg when instantiating subregs [PR120721]

https://gcc.gnu.org/g:8130a2ad91ca8571b099ba020443fadab7a688ca commit r16-1621-g8130a2ad91ca8571b099ba020443fadab7a688ca Author: Richard Sandiford Date: Mon Jun 23 08:46:27 2025 +0100 vregs: Use force_subreg when instantiating subregs [PR120721] In this PR, we started with:

[gcc r16-1537] aarch64: Add vec_set/extract for tuple modes [PR113027]

https://gcc.gnu.org/g:a63b97e918b8592d0f6af94c5355efc82a49e06d commit r16-1537-ga63b97e918b8592d0f6af94c5355efc82a49e06d Author: Richard Sandiford Date: Tue Jun 17 11:43:51 2025 +0100 aarch64: Add vec_set/extract for tuple modes [PR113027] We generated inefficient code for bitfiel

[gcc r16-1476] aarch64: Incorrect removal of ZA restore [PR120624]

https://gcc.gnu.org/g:8546265e2ee386ea8a4b2f9150ddfed32c9d15ea commit r16-1476-g8546265e2ee386ea8a4b2f9150ddfed32c9d15ea Author: Richard Sandiford Date: Thu Jun 12 12:10:39 2025 +0100 aarch64: Incorrect removal of ZA restore [PR120624] The PCS defines a lazy save scheme for managi

[gcc r16-1101] emit-rtl: Tweak validate_subreg ordered_p condition [PR120447]

https://gcc.gnu.org/g:5cb46d8fff07afee5ca828303544025e4a2e17b7 commit r16-1101-g5cb46d8fff07afee5ca828303544025e4a2e17b7 Author: Richard Sandiford Date: Wed Jun 4 13:36:51 2025 +0100 emit-rtl: Tweak validate_subreg ordered_p condition [PR120447] In the comment trail for PR119966,

[gcc r12-11118] aarch64: Fix CFA offsets in non-initial stack probes [PR119610]

https://gcc.gnu.org/g:e591109238fad430e94ae58f8f90b4bc9c8592a3 commit r12-8-ge591109238fad430e94ae58f8f90b4bc9c8592a3 Author: Richard Sandiford Date: Fri May 30 16:35:54 2025 +0100 aarch64: Fix CFA offsets in non-initial stack probes [PR119610] PR119610 is about incorrect CFI

[gcc r16-984] rtl-ssa: Reject non-address uses of autoinc regs [PR120347]

https://gcc.gnu.org/g:e322dff09d011f65f5cae4e95c3a24ccfae7b1e1 commit r16-984-ge322dff09d011f65f5cae4e95c3a24ccfae7b1e1 Author: Richard Sandiford Date: Fri May 30 09:36:35 2025 +0100 rtl-ssa: Reject non-address uses of autoinc regs [PR120347] As the rtl.texi documentation of RTX_A

[gcc r16-776] nds32: Avoid accessing beyond the operands[] array

https://gcc.gnu.org/g:a6ec398042c6054cbf2c08b646df98b63a9418d5 commit r16-776-ga6ec398042c6054cbf2c08b646df98b63a9418d5 Author: Richard Sandiford Date: Wed May 21 10:01:26 2025 +0100 nds32: Avoid accessing beyond the operands[] array This pattern used operands[2] to hold the shift

[gcc r16-788] genemit: Use a byte encoding to generate insns

https://gcc.gnu.org/g:d63c889d5cd3ef00ec5b0c3389448eab4f7d2b68 commit r16-788-gd63c889d5cd3ef00ec5b0c3389448eab4f7d2b68 Author: Richard Sandiford Date: Wed May 21 10:01:32 2025 +0100 genemit: Use a byte encoding to generate insns genemit has traditionally used open-coded gen_rtx_F

[gcc r16-784] genemit: Always track multiple uses of operands

https://gcc.gnu.org/g:8ebe8f5eff9fda40f22b9df7a0b8a6c2fdf5f8d7 commit r16-784-g8ebe8f5eff9fda40f22b9df7a0b8a6c2fdf5f8d7 Author: Richard Sandiford Date: Wed May 21 10:01:30 2025 +0100 genemit: Always track multiple uses of operands gen_exp has code to detect when the same operand i

[gcc r16-787] genemit: Avoid using gen_exp in output_add_clobbers

https://gcc.gnu.org/g:aca0cf1150d6f6be9ee451b5f91f505aef911f8e commit r16-787-gaca0cf1150d6f6be9ee451b5f91f505aef911f8e Author: Richard Sandiford Date: Wed May 21 10:01:31 2025 +0100 genemit: Avoid using gen_exp in output_add_clobbers output_add_clobbers emits code to add:

[gcc r16-786] genemit: Remove support for string operands

https://gcc.gnu.org/g:97d2686decc34400e585bbc725602757c91e3fbf commit r16-786-g97d2686decc34400e585bbc725602757c91e3fbf Author: Richard Sandiford Date: Wed May 21 10:01:31 2025 +0100 genemit: Remove support for string operands gen_exp currently supports the 's' (string) operand ty

[gcc r16-781] genemit: Factor out code common to insns and expands

https://gcc.gnu.org/g:5355568c75a99fc621e2008fa98626ad811678c5 commit r16-781-g5355568c75a99fc621e2008fa98626ad811678c5 Author: Richard Sandiford Date: Wed May 21 10:01:28 2025 +0100 genemit: Factor out code common to insns and expands Mostly to reduce cut-&-paste. gcc/

[gcc r16-783] genemit: Add a generator struct

https://gcc.gnu.org/g:88b849ffb9fc4b6de3786784b4c4b074758cc2a1 commit r16-783-g88b849ffb9fc4b6de3786784b4c4b074758cc2a1 Author: Richard Sandiford Date: Wed May 21 10:01:29 2025 +0100 genemit: Add a generator struct gen_exp now has quite a few arguments that need to be passed t

[gcc r16-785] genemit: Remove purported handling of location_ts

https://gcc.gnu.org/g:efbc8de515c71c27e881d425f8325e39f7b4f328 commit r16-785-gefbc8de515c71c27e881d425f8325e39f7b4f328 Author: Richard Sandiford Date: Wed May 21 10:01:30 2025 +0100 genemit: Remove purported handling of location_ts gen_exp had code to handle the 'L' operand forma

[gcc r16-778] sparc: Avoid operandN variables in .md files

https://gcc.gnu.org/g:35dd60935336eb574194f2fe2088133f34c8 commit r16-778-g35dd60935336eb574194f2fe2088133f34c8 Author: Richard Sandiford Date: Wed May 21 10:01:27 2025 +0100 sparc: Avoid operandN variables in .md files The automatically-generated gen_* routines take their

[gcc r16-782] genemit: Consistently use operand arrays in gen_* functions

https://gcc.gnu.org/g:02c3910f75ddae52dd59775bf9a6c4452bbdd0ac commit r16-782-g02c3910f75ddae52dd59775bf9a6c4452bbdd0ac Author: Richard Sandiford Date: Wed May 21 10:01:29 2025 +0100 genemit: Consistently use operand arrays in gen_* functions One slightly awkward part about emitti

[gcc r16-780] genemit: Add an internal queue

https://gcc.gnu.org/g:4fafb14e1f2ea068f2eb1a29ffb54d9984ab154d commit r16-780-g4fafb14e1f2ea068f2eb1a29ffb54d9984ab154d Author: Richard Sandiford Date: Wed May 21 10:01:28 2025 +0100 genemit: Add an internal queue An earlier version of this series wanted to collect information

[gcc r16-779] genemit: Use references rather than pointers

https://gcc.gnu.org/g:9b57e38e0ef26192ebb0e9e326ab3a9df06ee275 commit r16-779-g9b57e38e0ef26192ebb0e9e326ab3a9df06ee275 Author: Richard Sandiford Date: Wed May 21 10:01:27 2025 +0100 genemit: Use references rather than pointers This patch makes genemit.cc pass the md_rtx_info arou

[gcc r16-777] xstormy16: Avoid accessing beyond the operands[] array

https://gcc.gnu.org/g:856f6de5d19257e3c5802a250e7c749ca44beee3 commit r16-777-g856f6de5d19257e3c5802a250e7c749ca44beee3 Author: Richard Sandiford Date: Wed May 21 10:01:26 2025 +0100 xstormy16: Avoid accessing beyond the operands[] array The negsi2 C++ code writes to operands[2] e

[gcc r16-683] Make end_sequence return the insn sequence

https://gcc.gnu.org/g:84269eeecf3c31a7f6be1f210f5e6c38d0c01e31 commit r16-683-g84269eeecf3c31a7f6be1f210f5e6c38d0c01e31 Author: Richard Sandiford Date: Fri May 16 13:24:01 2025 +0100 Make end_sequence return the insn sequence The start_sequence/end_sequence interface was a big imp

[gcc r16-684] Automatic replacement of get_insns/end_sequence pairs

https://gcc.gnu.org/g:4dd13988c93c24ba3605f4b9cafc97515c34f2ac commit r16-684-g4dd13988c93c24ba3605f4b9cafc97515c34f2ac Author: Richard Sandiford Date: Fri May 16 13:24:01 2025 +0100 Automatic replacement of get_insns/end_sequence pairs This is the result of using a regexp to repl

[gcc r16-686] Manual tweak of some end_sequence callers

https://gcc.gnu.org/g:1b9c907a4c9f3a89970e5295c69aefa23a133958 commit r16-686-g1b9c907a4c9f3a89970e5295c69aefa23a133958 Author: Richard Sandiford Date: Fri May 16 13:24:03 2025 +0100 Manual tweak of some end_sequence callers This patch mops up obvious redundancies that weren't cau

[gcc r16-685] Automatic replacement of end_sequence/return pairs

https://gcc.gnu.org/g:e11ca9bc8c444b2a2fb12f8c1c2e4e203adeb39a commit r16-685-ge11ca9bc8c444b2a2fb12f8c1c2e4e203adeb39a Author: Richard Sandiford Date: Fri May 16 13:24:02 2025 +0100 Automatic replacement of end_sequence/return pairs This is the result of using a regexp to replace

[gcc r13-9645] aarch64: Fix CFA offsets in non-initial stack probes [PR119610]

https://gcc.gnu.org/g:89d186e6089ac3f0425f3a025068632ccc8d6eee commit r13-9645-g89d186e6089ac3f0425f3a025068632ccc8d6eee Author: Richard Sandiford Date: Fri May 9 12:07:56 2025 +0100 aarch64: Fix CFA offsets in non-initial stack probes [PR119610] PR119610 is about incorrect CFI ou

[gcc r14-11751] aarch64: Fix CFA offsets in non-initial stack probes [PR119610]

https://gcc.gnu.org/g:a9d390ab17d9395ce20e899ef0180052ed79d332 commit r14-11751-ga9d390ab17d9395ce20e899ef0180052ed79d332 Author: Richard Sandiford Date: Thu May 8 12:06:41 2025 +0100 aarch64: Fix CFA offsets in non-initial stack probes [PR119610] PR119610 is about incorrect CFI o

[gcc r16-336] Fix BZ 119317: named loops (C2y) with debug info

https://gcc.gnu.org/g:25921d664242f651ed8a25b3db55093a19a5ae7b commit r16-336-g25921d664242f651ed8a25b3db55093a19a5ae7b Author: Christopher Bazley Date: Thu May 1 22:00:42 2025 +0100 Fix BZ 119317: named loops (C2y) with debug info Named loops (C2y) could not previously be compile

[gcc r14-11705] testsuite: Force -mcmodel=small for gcc.target/aarch64/pr115258.c

https://gcc.gnu.org/g:fd9d35f68eabb7cdb250fde1d1ce2010384182a4 commit r14-11705-gfd9d35f68eabb7cdb250fde1d1ce2010384182a4 Author: Richard Sandiford Date: Wed Apr 30 16:40:44 2025 +0100 testsuite: Force -mcmodel=small for gcc.target/aarch64/pr115258.c The test implicitly assumed th

[gcc r15-9606] testsuite: Force -mcmodel=small for gcc.target/aarch64/pr115258.c

https://gcc.gnu.org/g:c9d4d3ba15c55e108f5f9a28d2609a698634a5db commit r15-9606-gc9d4d3ba15c55e108f5f9a28d2609a698634a5db Author: Richard Sandiford Date: Wed Apr 30 16:29:54 2025 +0100 testsuite: Force -mcmodel=small for gcc.target/aarch64/pr115258.c The test implicitly assumed the

[gcc r16-310] testsuite: Force -mcmodel=small for gcc.target/aarch64/pr115258.c

https://gcc.gnu.org/g:3584aab37f54bcd220c7061568af777e37f4f6ed commit r16-310-g3584aab37f54bcd220c7061568af777e37f4f6ed Author: Richard Sandiford Date: Wed Apr 30 16:28:52 2025 +0100 testsuite: Force -mcmodel=small for gcc.target/aarch64/pr115258.c The test implicitly assumed the

[gcc r16-286] simplify-rtx: Combine bitwise operations in more cases

https://gcc.gnu.org/g:d84fbc516ea57de7e88fce76ff6f342ee808c02e commit r16-286-gd84fbc516ea57de7e88fce76ff6f342ee808c02e Author: Pengfei Li Date: Tue Apr 29 19:14:42 2025 +0100 simplify-rtx: Combine bitwise operations in more cases This patch transforms RTL expressions of the form

[gcc r15-9598] aarch64: Fix CFA offsets in non-initial stack probes [PR119610]

https://gcc.gnu.org/g:68a75e3c0dcdb883cc96b626b541da20ab4df2f2 commit r15-9598-g68a75e3c0dcdb883cc96b626b541da20ab4df2f2 Author: Richard Sandiford Date: Tue Apr 29 16:07:37 2025 +0100 aarch64: Fix CFA offsets in non-initial stack probes [PR119610] PR119610 is about incorrect CFI o

[gcc r16-195] simplify-rtx: Split out native_decode_int

https://gcc.gnu.org/g:ef32bd8c866a1b8a97f627fad44a42f29757c816 commit r16-195-gef32bd8c866a1b8a97f627fad44a42f29757c816 Author: Richard Sandiford Date: Mon Apr 28 14:40:09 2025 +0100 simplify-rtx: Split out native_decode_int native_decode_rtx handles integer modes by building up a

  1   2   3   4   5   >