[Bug target/115789] gcc miscompile itself with CFLAGS -O3 -march=rv64gcv_zvl256b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115789 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/116242] [meta-bug] Tracker for zvl issues in RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116242 Bug 116242 depends on bug 115789, which changed state. Bug 115789 Summary: gcc miscompile itself with CFLAGS -O3 -march=rv64gcv_zvl256b https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115789 What|Removed |Added --

[Bug target/117011] RISC-V: Logic overlap in IF_THEN_ELSE case for instruction cost calculation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117011 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |WONTFIX Status|UNCONFIRMED

[Bug rtl-optimization/116915] [15 Regression] wrong code at -O{s,2,3} on x86_64-linux-gnu

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116915 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |DUPLICATE Status|ASSIGNED

[Bug rtl-optimization/116488] [15 Regression] wrong code at -O{s,2,3} with "-fno-forward-propagate" on x86_64-linux-gnu

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116488 --- Comment #6 from Jeffrey A. Law --- *** Bug 116915 has been marked as a duplicate of this bug. ***

[Bug rtl-optimization/116488] [15 Regression] wrong code at -O{s,2,3} with "-fno-forward-propagate" on x86_64-linux-gnu

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116488 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug rtl-optimization/116488] [15 Regression] wrong code at -O{s,2,3} with "-fno-forward-propagate" on x86_64-linux-gnu

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116488 --- Comment #5 from Jeffrey A. Law --- *** Bug 117226 has been marked as a duplicate of this bug. ***

[Bug rtl-optimization/117226] [15 regression] wrong code at -O{s,2,3} with "-fno-tree-forwprop" on x86_64-linux-gnu with ext-dce since r15-1901-g98914f9eba5f19

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117226 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |DUPLICATE Status|ASSIGNED

[Bug target/116425] RISC-V missed optimization: vector lowering along lmul boundaries

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116425 --- Comment #3 from Jeffrey A. Law --- The vector loads you're referring to always load a full vector register and do not need a configuration to be set by vsetvl. There's also move instructions that copy from one vector register to another with

[Bug target/116615] Investigate LOGICAL_OP_NON_SHORT_CIRCUIT for RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116615 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug middle-end/116926] [15 Regression] Recent changes in dot-product causing ICE on c6x port

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116926 Jeffrey A. Law changed: What|Removed |Added Status|WAITING |NEW --- Comment #5 from Jeffrey A. Law

[Bug target/117111] [SH] delay slot is filled with wrong instruction

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117111 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #5

[Bug testsuite/117261] New test cases from r15-4532-g36e91df7716d34 fail

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117261 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/117353] [15 regression] RISC-V: ICE when building libcrypt since r15-3228-g771256bcb9ddc4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117353 --- Comment #3 from Jeffrey A. Law --- That doesn't make sense. The can_create_pseudo_p() check should have prevented this from matching once reload has started. Does the insn exist in the .ira dump, and if so, what is its RTL form?

[Bug target/117316] [15 regression] gcc/config/riscv/riscv.cc:479:1: error: could not convert ‘...’ from ‘’ to ‘const riscv_tune_param’ since r15-4589-g078f7c4f1fcf4d

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117316 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug rtl-optimization/117476] [15 regression] bad generated code at -O1 since r15-4991-g69bd93c167fefb

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117476 --- Comment #24 from Jeffrey A. Law --- My plan is to revert the problematic change tomorrow unless Alexey has a patch ready. There's no sense in having folks keep stumbling over this while Alexey is cobbling together a fix. It's not a reflec

[Bug tree-optimization/117282] Miss optimization to eliminate strlen computation

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117282 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #4

[Bug rtl-optimization/117476] [15 regression] bad generated code at -O1 since r15-4991-g69bd93c167fefb

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117476 --- Comment #30 from Jeffrey A. Law --- I've reverted the patch and given Alexey some guidance on how to fix the testcase from Zdenek. Alexey, I'd recommend including Zdenek's testcase as well. Note that it uses 128bit objects, so in the test y

[Bug rtl-optimization/117476] [15 regression] bad generated code at -O1 since r15-4991-g69bd93c167fefb

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117476 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug rtl-optimization/117360] [15 regression] ext-dce.cc:573:15: runtime error: shift exponent 127 is too large for 64-bit type 'long long unsigned int'

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117360 --- Comment #3 from Jeffrey A. Law --- What's interesting is I did a bootstrap with ubsan a while back to chase down this stuff. Could be something recently introduced or a path we didn't trigger before. Regardless I'll case it down. Yes, we

[Bug target/117353] [15 regression] RISC-V: ICE when building libcrypt since r15-3228-g771256bcb9ddc4

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117353 --- Comment #6 from Jeffrey A. Law --- So my approach would be to note the insn number, then set a conditional breakpoint in make_insn_raw (after it initializes INSN_UID in the new insn). The condition would be insn->u2.insn_uid == or somethi

[Bug target/111926] RISC-V: Use vsetvl insn replace csrr vlenb insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111926 Jeffrey A. Law changed: What|Removed |Added Keywords||easyhack --- Comment #6 from Jeffrey A

[Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Sta

[Bug target/111926] RISC-V: Use vsetvl insn replace csrr vlenb insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111926 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #4

[Bug middle-end/111621] [RISC-V] Bad register allocation in vadd.vi may cause operational error

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111621 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Resolut

[Bug target/116592] illegal operands th.vsetvli zero,0,e32,m8 with -O2 -O3 when compiling for risc-v xtheadvector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116592 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED CC|

[Bug target/116594] [meta-bug] xtheadvector brokeness

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116594 Bug 116594 depends on bug 116592, which changed state. Bug 116592 Summary: illegal operands th.vsetvli zero,0,e32,m8 with -O2 -O3 when compiling for risc-v xtheadvector https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116592 What|Rem

[Bug target/116693] [RISC-V] @tlsdesc generates duplicate assembler labels

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116693 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/116715] RISC-V: Miscompile at -O2 with -march=rv64id_zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116715 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/116111] RISC-V: 'd' extension allowed with -mabi=ilp32e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116111 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/113980] risc-v: unnecessary sign-extend after lw with volatile, and more

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113980 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/108038] GCC generates poor code for select of consecutive constants on riscv-64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108038 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug middle-end/116926] New: [15 Regression] Recent changes in dot-product causing ICE on c6x port

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116926 Bug ID: 116926 Summary: [15 Regression] Recent changes in dot-product causing ICE on c6x port Product: gcc Version: unknown Status: UNCONFIRMED Severity: norma

[Bug rtl-optimization/116919] extra zext for bitwise operations with a constant

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116919 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug target/112109] Missing riscv vectorized strcmp (and other) expanders

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112109 --- Comment #7 from Jeffrey A. Law --- We could close and open an new issue to honor TARGET_MAX_LMUL, or just reuse this one after an adjustment of the title. No strong preference.

[Bug rtl-optimization/116919] extra zext for bitwise operations with a constant

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116919 --- Comment #3 from Jeffrey A. Law --- I don't know your extension set or pipeline, but one additional thing that might improve things further would be to adjust the risc-v expansion code to alternate between a table lookup and a clmul variant.

[Bug rtl-optimization/112398] Suboptimal code generation for xor pattern on subreg

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112398 --- Comment #8 from Jeffrey A. Law --- So Alexey's patch helps the first case, generating the more efficient lbu+xori sequence. I suspect it's not helping the 2nd case because the constant is going to be out of range. Given the 2nd case also s

[Bug target/117649] [15 regression] [RISC-V] binutils miscompiled by r15-4224-gc8957c8779954c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117649 --- Comment #3 from Jeffrey A. Law --- Thanks a ton of that Andreas!

[Bug target/117595] ICE: SIGSEGV in mark_jump_label_1 (jump.cc:1051) with -mbig-endian and _Atomic enum

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117595 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/117649] [15 regression] [RISC-V] binutils miscompiled by r15-4224-gc8957c8779954c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117649 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2024-11-19 Status|UNCONFIR

[Bug target/116590] unrecognized opcode th.vmv8r.v th.vfrec7.v when compiling for risc-v xtheadvector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116590 Jeffrey A. Law changed: What|Removed |Added CC||kito at gcc dot gnu.org --- Comment #5

[Bug rtl-optimization/116915] [15 Regression] wrong code at -O{s,2,3} on x86_64-linux-gnu

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116915 --- Comment #5 from Jeffrey A. Law --- Thanks for cleaning up those issues. 16bit testing just doesn't get as much attention as the more mainstream targets.

[Bug target/117649] [15 regression] [RISC-V] binutils miscompiled by r15-4224-gc8957c8779954c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117649 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/117669] RISC-V:The 'VEEWTRUNC4' iterator 'RVVMF2BF' type condition error

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117669 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/117690] [15 Regression] RISC-V: Constant is miscompiled by zba extension

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117690 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org

[Bug target/117690] [15 Regression] RISC-V: Constant is miscompiled by zba extension

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117690 --- Comment #3 from Jeffrey A. Law --- Looks like it's missing the shift to move bits into the upper half.

[Bug target/117628] [15 Regression] arm/linux-atomic.c contains invalid C23 (trying to typedef bool)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117628 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/116594] [meta-bug] xtheadvector brokeness

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116594 Bug 116594 depends on bug 116591, which changed state. Bug 116591 Summary: internal compiler error: in extract_insn when compiling for risc-v xtheadvector https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116591 What|Removed

[Bug target/116591] internal compiler error: in extract_insn when compiling for risc-v xtheadvector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116591 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/117483] [15 Regression] ICE: in merge, at config/riscv/riscv-vsetvl.cc:2106

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117483 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/117616] frv: may need adaptation for C23 varargs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117616 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #1

[Bug rtl-optimization/112398] Suboptimal code generation for xor pattern on subreg

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112398 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/111600] [14/15 Regression] RISC-V bootstrap time regression

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111600 --- Comment #40 from Jeffrey A. Law --- Just an FYI. My BPI will pick this up and bootstrap it on Wednesday. So we should be able to see concretely if it improved things.

[Bug target/116425] RISC-V missed optimization: vector lowering along lmul boundaries

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116425 --- Comment #4 from Jeffrey A. Law --- Wouldn't these cases be better handled doing the scalar load, then splat it across the vector, then the stores? No gather needed at all.

[Bug bootstrap/80677] LIMITS_H_TEST is wrong

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80677 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #7 f

[Bug tree-optimization/117895] [15 regression] ICE in operand_subword_force since r15-5850-g4d2b9202fe94c5

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117895 --- Comment #1 from Jeffrey A. Law --- Ugh. libgo + sparc + solaris 2. Hopefully I can find a way to reproduce this.

[Bug middle-end/114087] RISC-V optimization on checking certain bits set ((x & mask) == val)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114087 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Ever confirmed|0

[Bug tree-optimization/117997] [15 regression] libgo regressions on aarch64 after g:4d2b9202fe94c54e63fb07d48293a78da3d82532

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117997 --- Comment #2 from Jeffrey A. Law --- Definitely the bzip.go bits as opposed to the crc32.go bits. No other insights yet.

[Bug target/115375] [15 Regression] RISCV scan failures since 2024-05-04

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115375 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/118036] [15 Regression] RISC-V: gcc.dg/vect/vect-alias-check-1[12].c abort

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118036 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug tree-optimization/106297] [12/13/14 Regression] stringop-overflow misbehaviour on atomic since r12-4725-g88b504b7a8c5affb

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106297 Jeffrey A. Law changed: What|Removed |Added Summary|[12/13/14/15 Regression]|[12/13/14 Regression]

[Bug middle-end/107991] [12/13/14 Regression] Extra mov instructions with ternary on x86

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107991 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Summ

[Bug target/100378] [12/13/14/15 Regression] arm64: lsl + asr used instead of sxth

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100378 Jeffrey A. Law changed: What|Removed |Added See Also||https://gcc.gnu.org/bugzill

[Bug tree-optimization/117997] [15 regression] libgo regressions on aarch64 after g:4d2b9202fe94c54e63fb07d48293a78da3d82532

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117997 --- Comment #1 from Jeffrey A. Law --- I'm highly confident the problem is in the libgo DSO and not in the testcode itself (I can run the test binary with the system libgo DSO and it works). Given the error message I would expect the problem is

[Bug rtl-optimization/107455] Suboptimal codegen for some branch-on-zero cases

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107455 Jeffrey A. Law changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassigned

[Bug tree-optimization/117997] [15 regression] libgo regressions on aarch64 after g:4d2b9202fe94c54e63fb07d48293a78da3d82532

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117997 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Ever confirmed|0

[Bug testsuite/118055] [15 Regression] gcc.dg/tree-ssa/pr83403-1.c and -2 for CRIS and m68k since r15-6097-gee2f19b0937b5e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118055 Jeffrey A. Law changed: What|Removed |Added Status|WAITING |RESOLVED Resolution|---

[Bug testsuite/118055] [15 Regression] gcc.dg/tree-ssa/pr83403-1.c and -2 for CRIS and m68k since r15-6097-gee2f19b0937b5e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118055 --- Comment #12 from Jeffrey A. Law --- WRT other targets. I do test various other targets, but that's mostly to find generic bugs. I could certainly send results to the lists and have serious pondered it before, but never bothered to set up t

[Bug target/118137] riscv64: sub-word atomic OR with -1 affects surrounding bytes

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118137 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/117286] [RISC-V] internal compiler error: Segmentation fault `__riscv_vlmul_ext_v_f16mf2_f16m1`

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117286 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/116715] RISC-V: Miscompile at -O2 with -march=rv64id_zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116715 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/114222] gcc.c-torture/execute/builtin-bitops-1.c fails for H8/300

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114222 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |INVALID Status|UNCONFIRMED

[Bug target/106544] riscv_print_operand does not check to see if the operands are valid to do INTVAL on them

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106544 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/113828] ICE: in riscv_expand_mult_with_const_int, at config/riscv/riscv.cc:2587 with -march=rv64ifv and vfloat32m1_t/vfloat32m4_t function args

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113828 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/116720] [13/14 Regression] RISC-V: Unrecognizable insn with xtheadmemidx on rv32

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116720 Jeffrey A. Law changed: What|Removed |Added Summary|[13/14/15 Regression] |[13/14 Regression] RISC-V:

[Bug target/108764] [RISCV] Cost model for RVB is too aggressive

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108764 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/116715] RISC-V: Miscompile at -O2 with -march=rv64id_zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116715 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org --- Comm

[Bug target/117906] [15 regression] RISC-V: gfortran.dg/sizeof_6.f90 -O1 timeout since r15-5897-g31250baf814

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117906 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/115500] RISC-V: Performance regression on 1bit test

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115500 Jeffrey A. Law changed: What|Removed |Added Status|WAITING |RESOLVED Resolution|---

[Bug tree-optimization/110538] [14 Regression] Dead Code Elimination Regression since r14-368-ge1366a7e4ce

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110538 Jeffrey A. Law changed: What|Removed |Added Summary|[14/15 Regression] Dead |[14 Regression] Dead Code

[Bug tree-optimization/110361] [13 Regression] Missed Dead Code Elimination when using __builtin_unreachable since r13-2020-g16b013c9d9b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110361 Jeffrey A. Law changed: What|Removed |Added Summary|[13/14/15 Regression] |[13 Regression] Missed Dead

[Bug target/117953] [15 Regression] GCC miscompile rvv intrinsics at `-O2` and `-O3`, missing `csrwi` to modify `vxrm`

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117953 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |WORKSFORME Status|UNCONFIR

[Bug testsuite/116986] FAIL: gcc.dg/torture/pr115387-2.c -O0 (test for excess errors)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116986 Jeffrey A. Law changed: What|Removed |Added CC|law at gcc dot gnu.org | --- Comment #1 from Jeffrey A.

[Bug target/115849] RISC-V should improve handling of -0.0 when -fno-signed-zeros is enabled

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115849 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/110748] RISC-V: optimize store of DF 0.0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110748 --- Comment #17 from Jeffrey A. Law --- *** Bug 115849 has been marked as a duplicate of this bug. ***

[Bug target/116720] [13/14/15 Regression] RISC-V: Unrecognizable insn with xtheadmemidx on rv32

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116720 Jeffrey A. Law changed: What|Removed |Added Assignee|cmuellner at gcc dot gnu.org |law at gcc dot gnu.org --- Comm

[Bug target/118197] ICE: SIGSEGV in emit_move_insn (expr.cc:4635) at -O1 and above

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118197 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/118170] ICE: in riscv_sched_variable_issue, at config/riscv/riscv.cc:9790 with -mcpu=tt-ascalon-d8 and _Float16

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118170 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Priority|P3

[Bug target/116308] ICE while compiling _Atomic _Float16 for riscv64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116308 --- Comment #2 from Jeffrey A. Law --- *** Bug 118197 has been marked as a duplicate of this bug. ***

[Bug target/118197] ICE: SIGSEGV in emit_move_insn (expr.cc:4635) at -O1 and above

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118197 Jeffrey A. Law changed: What|Removed |Added Resolution|FIXED |DUPLICATE --- Comment #3 from Jeffrey

[Bug rtl-optimization/118153] Wrong code generated due to selective scheduler on RISC-V target

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118153 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P4 --- Comment #1 from Jeffrey A. Law

[Bug target/117835] wrong code with -O -favoid-store-forwarding -mno-push-args --param=store-forwarding-max-distance=0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117835 --- Comment #3 from Jeffrey A. Law --- *** Bug 117872 has been marked as a duplicate of this bug. ***

[Bug rtl-optimization/117872] wrong code with -O -maccumulate-outgoing-args --param=store-forwarding-max-distance=1000 -favoid-store-forwarding

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117872 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED CC|

[Bug rtl-optimization/117836] [meta-bug] favoid-store-forwarding issues

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117836 Bug 117836 depends on bug 117872, which changed state. Bug 117872 Summary: wrong code with -O -maccumulate-outgoing-args --param=store-forwarding-max-distance=1000 -favoid-store-forwarding https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117872

[Bug target/106517] RISC-V: Inefficient Generated Code for Floating Point to Integer Rounds

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106517 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug tree-optimization/85186] jump threading can rotate loops affecting loop form, and causing vectorization not to happen

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85186 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug tree-optimization/53947] [meta-bug] vectorizer missed-optimizations

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53947 Bug 53947 depends on bug 85186, which changed state. Bug 85186 Summary: jump threading can rotate loops affecting loop form, and causing vectorization not to happen https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85186 What|Removed

[Bug tree-optimization/91645] Missed optimization with sqrt(x*x)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91645 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug middle-end/24639] [meta-bug] bug to track all Wuninitialized issues

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=24639 Bug 24639 depends on bug 82090, which changed state. Bug 82090 Summary: Bogus warning: ‘magic_p’ may be used uninitialized in this function [-Wmaybe-uninitialized] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82090 What|Removed

[Bug tree-optimization/82090] Bogus warning: ‘magic_p’ may be used uninitialized in this function [-Wmaybe-uninitialized]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82090 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

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