[Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

2024-09-22 Thread law at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org Sta

[Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

2024-07-18 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456 --- Comment #7 from GCC Commits --- The releases/gcc-14 branch has been updated by Kito Cheng : https://gcc.gnu.org/g:4db38759dcae7426ea5ce4432afe97bdd2d87ac8 commit r14-10467-g4db38759dcae7426ea5ce4432afe97bdd2d87ac8 Author: Pan Li Date: F

[Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

2024-07-18 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456 --- Comment #6 from GCC Commits --- The releases/gcc-14 branch has been updated by Kito Cheng : https://gcc.gnu.org/g:87346ed74cc069d133918e28761fa8ef3c8ec874 commit r14-10466-g87346ed74cc069d133918e28761fa8ef3c8ec874 Author: Pan Li Date: T

[Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

2024-06-14 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456 --- Comment #5 from GCC Commits --- The master branch has been updated by Pan Li : https://gcc.gnu.org/g:c2c61d8902dbda017b1647252d17bce141493433 commit r15-1327-gc2c61d8902dbda017b1647252d17bce141493433 Author: Pan Li Date: Fri Jun 14 14:5

[Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

2024-06-13 Thread sh.chiang04 at gmail dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456 --- Comment #4 from Monk Chiang --- The test case, if add this option: -mrvv-vector-bits=zvl It has a new internal compiler error. compress_run-2.c:25:1: error: unrecognizable insn: 25 | } | ^ (insn 30 29 31 2 (set (reg:HF 156 [ _2 ])

[Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

2024-06-13 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456 --- Comment #3 from GCC Commits --- The master branch has been updated by Pan Li : https://gcc.gnu.org/g:3dac1049c1211e6d06c2536b86445a6334c3866d commit r15-1243-g3dac1049c1211e6d06c2536b86445a6334c3866d Author: Pan Li Date: Thu Jun 13 15:2

[Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

2024-06-12 Thread pan2.li at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456 --- Comment #2 from Li Pan --- According to the ISA, Zvfhmin only contains 2 insns, quote as below " The Zvfhmin extension provides minimal support for vectors of IEEE 754-2008 binary16 values, adding conversions to and from binary32. When the

[Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

2024-06-12 Thread pan2.li at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456 --- Comment #1 from Li Pan --- Ack, will take care of it.