[Bug target/115456] RISC-V: ICE: unrecognizable insn with march=rv64gcv_zvfhmin

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115456

--- Comment #6 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-14 branch has been updated by Kito Cheng <k...@gcc.gnu.org>:

https://gcc.gnu.org/g:87346ed74cc069d133918e28761fa8ef3c8ec874

commit r14-10466-g87346ed74cc069d133918e28761fa8ef3c8ec874
Author: Pan Li <pan2...@intel.com>
Date:   Thu Jun 13 15:26:59 2024 +0800

    RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch

    We have vec_extract pattern which takes ZVFHMIN as the mode
    iterator of the VLS mode.  Aka V_VLS.  But it will expand to
    pred_extract_first pattern which takes the ZVFH as the mode
    iterator of the VLS mode.  AKa V_VLSF.  The mismatch will
    result in one ICE similar as below:

    error: unrecognizable insn:
       27 | }
          | ^
    (insn 19 18 20 2 (set (reg:HF 150 [ _13 ])
            (unspec:HF [
                    (vec_select:HF (reg:V4HF 134 [ _1 ])
                        (parallel [
                                (const_int 0 [0])
                            ]))
                    (reg:SI 67 vtype)
                ] UNSPEC_VPREDICATE)) "compress_run-2.c":24:5 -1
         (nil))
    during RTL pass: vregs
    compress_run-2.c:27:1: internal compiler error: in extract_insn, at
    recog.cc:2812
    0x1a627ef _fatal_insn(char const*, rtx_def const*, char const*, int,
    char const*)
            ../../../gcc/gcc/rtl-error.cc:108
    0x1a62834 _fatal_insn_not_found(rtx_def const*, char const*, int, char
    const*)
            ../../../gcc/gcc/rtl-error.cc:116
    0x1a0f356 extract_insn(rtx_insn*)
            ../../../gcc/gcc/recog.cc:2812
    0x159ee61 instantiate_virtual_regs_in_insn
            ../../../gcc/gcc/function.cc:1612
    0x15a04aa instantiate_virtual_regs
            ../../../gcc/gcc/function.cc:1995
    0x15a058e execute
            ../../../gcc/gcc/function.cc:2042

    This patch would like to fix this issue by align the mode
    iterator restriction to ZVFH.

    The below test suites are passed for this patch.
    1. The rv64gcv fully regression test.
    2. The rv64gcv build with glibc.

            PR target/115456

    gcc/ChangeLog:

            * config/riscv/autovec.md: Take ZVFH mode iterator instead of
            the ZVFHMIN for the alignment.
            * config/riscv/vector-iterators.md: Add 2 new iterator
            V_VLS_ZVFH and VLS_ZVFH.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr115456-1.c: New test.

    Signed-off-by: Pan Li <pan2...@intel.com>
    (cherry picked from commit 3dac1049c1211e6d06c2536b86445a6334c3866d)