[Bug target/109436] New: AArch64: suboptimal codegen in 128 bit constant stores

2023-04-06 Thread sinan.lin at linux dot alibaba.com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109436 Bug ID: 109436 Summary: AArch64: suboptimal codegen in 128 bit constant stores Product: gcc Version: 13.0 Status: UNCONFIRMED Severity: normal Priority: P3 Comp

[Bug target/109416] Missed constant propagation cases after reload

2023-04-06 Thread sinan.lin at linux dot alibaba.com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109416 --- Comment #3 from Sinan --- Hi Andrew, Thank you for taking the time to explain the issue. I appreciate it. I think the issue between init/init2 and init3 might be different. Regarding init3, any 32-bit backend attempting to split a complex

[Bug rtl-optimization/109416] New: Missed constant propagation cases after reload

2023-04-04 Thread sinan.lin at linux dot alibaba.com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109416 Bug ID: 109416 Summary: Missed constant propagation cases after reload Product: gcc Version: 13.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: r

[Bug target/109414] RISC-V: unnecessary sext.w in rv64

2023-04-04 Thread sinan.lin at linux dot alibaba.com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109414 --- Comment #4 from Sinan --- (In reply to Andrew Pinski from comment #1) > Actually this more related to WORD_REGISTER_OPERATIONS . > > (insn 7 4 8 2 (set (reg:SI 77) > (plus:SI (subreg/s/u:SI (reg/v:DI 74 [ x ]) 0) > (cons

[Bug target/109414] RISC-V: unnecessary sext.w in rv64

2023-04-04 Thread sinan.lin at linux dot alibaba.com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109414 --- Comment #2 from Sinan --- commit 23d9f62c50d935462ecda5516746037a474c25cd looks like a solution for this. like adding a new pattern for `not` ``` (define_insn "*one_cmpl_subreg" [(set (match_operand:DI 0 "register_operand" "=r")

[Bug target/109414] New: RISC-V: unnecessary sext.w in rv64

2023-04-04 Thread sinan.lin at linux dot alibaba.com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109414 Bug ID: 109414 Summary: RISC-V: unnecessary sext.w in rv64 Product: gcc Version: 13.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/108764] [RISCV] Cost model for RVB is too aggressive

2023-02-12 Thread sinan.lin at linux dot alibaba.com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108764 --- Comment #5 from Sinan --- (In reply to Kito Cheng from comment #3) > > I think one solution is to change the cost model of such complex > > instructions to the sum of the cost for each part. E.g. > > cost for shNadd = COSTS_N_INSNS (SINGLE

[Bug target/108764] [RISCV] Cost model for RVB is too aggressive

2023-02-12 Thread sinan.lin at linux dot alibaba.com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108764 --- Comment #4 from Sinan --- (In reply to Andrew Pinski from comment #2) > sllia4,a2,3 > sh3add a5,a2,a0 > > vs > sllia2,a2,3 > add a5,a0,a2 > > I think the first one is better really because you have

[Bug target/108764] [RISCV] Cost model for RVB is too aggressive

2023-02-11 Thread sinan.lin at linux dot alibaba.com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108764 Sinan changed: What|Removed |Added Target||riscv --- Comment #1 from Sinan --- In the giv

[Bug target/108764] New: [RISCV] Cost model for RVB is too aggressive

2023-02-11 Thread sinan.lin at linux dot alibaba.com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108764 Bug ID: 108764 Summary: [RISCV] Cost model for RVB is too aggressive Product: gcc Version: 13.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: tar

[Bug rtl-optimization/107455] New: Suboptimal codegen for some branch-on-zero cases

2022-10-29 Thread sinan.lin at linux dot alibaba.com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107455 Bug ID: 107455 Summary: Suboptimal codegen for some branch-on-zero cases Product: gcc Version: 13.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: