https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108764
--- Comment #5 from Sinan <sinan.lin at linux dot alibaba.com> --- (In reply to Kito Cheng from comment #3) > > I think one solution is to change the cost model of such complex > > instructions to the sum of the cost for each part. E.g. > > cost for shNadd = COSTS_N_INSNS (SINGLE_SHIFT_COST) + COSTS_N_INSNS (1) # > > cost of addition > > Some RISC-V core implementation did has one cycle for shNadd operation as I > know, but I know it's not true for every implementation. Thanks for the info. Interestingly, the shNadd-like instructions(add reg1, reg2, reg3, lsl #N) in AArch64/neoverse-n1 are also one cycle operations(https://developer.arm.com/documentation/pjdoc466751330-9707/latest), but the cost model for them is different from the one in riscv backend(AArch64 doesn't generate add r1, r2, r3, lsl #3 for the given test case). > Anyway, it's really uarch dependent, so I would prefer keep as it for now, > and then extend the cost model function to easier handle different uarch > (-mtune) when GCC 14 is open. Agree.
