--- Comment #16 from sergeid at il dot ibm dot com 2008-12-21 07:44 ---
(In reply to comment #15)
> Re. comment #14: Yes, I suppose so. Why do you want to remove gcse-las from
> mainline. Not that I'm against it -- ideally RTL gcse.c would not work on
> memory at all an
--- Comment #14 from sergeid at il dot ibm dot com 2008-12-15 07:17 ---
Ok, since this case is the only one where RTL PRE (gcse-las) improves
performance and it can be dealt with at the TreeSSA level, it should be ok to
remove gcse-las from mainline and keep this PR open?
--
http
--- Comment #12 from sergeid at il dot ibm dot com 2008-12-08 11:53 ---
I have to mention that tree PRE still don't catch this LOAD with -O3.
Though the patch Richard posted does the job.
(In reply to comment #1)
> It works with -O3 (with partial-partial PRE enabled). At leas
--- Comment #10 from sergeid at il dot ibm dot com 2008-12-08 10:08 ---
Subject: Re: TreeSSA-PRE load after store
misoptimization
Sorry, forgot to attach the patch.(See attached file:
gcse-las-counter.patch)
--- Comment #11 from sergeid at il dot ibm dot com 2008-12-08 10:08
--- Comment #9 from sergeid at il dot ibm dot com 2008-12-08 10:03 ---
Subject: Re: TreeSSA-PRE load after store
misoptimization
Can you post your gcc configuration options?
I've created and attached a little patch which adds some more information
to dump file. Can you apply i
--- Comment #7 from sergeid at il dot ibm dot com 2008-12-04 17:54 ---
Subject: Re: TreeSSA-PRE load after store
misoptimization
You're right, it worked for me only on powerpc. This is RTL snippet
_before_ elimination (load + xor + store):
...
(insn 20 19 21 5 ../loop.c:10
ned at gcc dot gnu dot org
ReportedBy: sergeid at il dot ibm dot com
GCC build triplet: powerpc
GCC host triplet: powerpc
GCC target triplet: powerpc
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=38401
