------- Comment #7 from sergeid at il dot ibm dot com 2008-12-04 17:54 -------
Subject: Re: TreeSSA-PRE load after store
misoptimization
You're right, it worked for me only on powerpc. This is RTL snippet
_before_ elimination (load + xor + store):
...
(insn 20 19 21 5 ../loop.c:10 (set (reg:SI 128)
(mem:SI (reg/v/f:SI 123 [ res ]) [2 S4 A32])) 324
{*movsi_internal1} (nil))
(insn 21 20 22 5 ../loop.c:10 (set (reg:SI 129)
(xor:SI (reg:SI 128)
(const_int 234 [0xea]))) 139 {*boolsi3_internal1} (nil))
(insn 22 21 23 5 ../loop.c:10 (set (mem:SI (reg/v/f:SI 123 [ res ]) [2 S4
A32])
(reg:SI 129)) 324 {*movsi_internal1} (nil)):
...
And this is _after_ (xor + store only):
...
(insn 21 19 22 5 ../loop.c:10 (set (reg:SI 131)
(xor:SI (reg:SI 131)
(const_int 234 [0xea]))) 139 {*boolsi3_internal1}
(expr_list:REG_DEAD (reg:SI 131)
(nil)))
(insn 22 21 23 5 ../loop.c:10 (set (mem:SI (reg/v/f:SI 123 [ res ]) [2 S4
A32])
(reg:SI 131)) 324 {*movsi_internal1} (expr_list:REG_DEAD (reg:SI
129)])
(nil)))
...
On x86 it produces complex set instructions:
...
(insn 18 17 19 5 ../loop.c:10 (parallel [
(set (mem:SI (reg/v/f:DI 62 [ res ]) [2 S4 A32])
(xor:SI (mem:SI (reg/v/f:DI 62 [ res ]) [2 S4 A32])
(const_int 234 [0xea])))
(clobber (reg:CC 17 flags))
]) 417 {*xorsi_1} (expr_list:REG_UNUSED (reg:CC 17 flags)])
(nil)))
...
and that's why (probably) GCSE can't optimize it.
PS. BTW, I _do_ compile it with "-O3" and tree PRE doesn't catch it.
"steven at gcc dot gnu dot org" <[EMAIL PROTECTED]> wrote on
04/12/2008 19:08:57:
> I do not see RTL PRE catch this on ia64, with or without -fgcse-las.
>
> Can you show, please, the RTL dumps before and after GCSE?
>
>
> --
>
>
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=38401
>
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--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=38401
