[Bug target/118119] [15 regression] RISC-V: gcc.c-torture/execute/va-arg-24.c zvl256b failure

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118119 Edwin Lu changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug tree-optimization/118405] [15 regression] RISC-V: ICE in verify_gimple during GIMPLE pass vect

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118405 --- Comment #1 from Edwin Lu --- >From my tinkering with the code, I've only really been able to bypass the added check as a potential "solution". For example, something like this essentially keeps the guaranteed `ltype = vectype` update regardl

[Bug tree-optimization/118405] New: [15 regression] RISC-V: ICE in verify_gimple during GIMPLE pass vect

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118405 Bug ID: 118405 Summary: [15 regression] RISC-V: ICE in verify_gimple during GIMPLE pass vect Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/118363] [15 regression] RISC-V: excess errors in c-c++-common/gomp/dispatch-11.c with zvls > 128b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118363 Edwin Lu changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/118363] New: [15 regression] RISC-V: excess errors in c-c++-common/gomp/dispatch-11.c with zvls > 128

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118363 Bug ID: 118363 Summary: [15 regression] RISC-V: excess errors in c-c++-common/gomp/dispatch-11.c with zvls > 128 Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug target/118119] New: [15 regression] RISC-V: gcc.c-torture/execute/va-arg-24.c zvl256b failure

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118119 Bug ID: 118119 Summary: [15 regression] RISC-V: gcc.c-torture/execute/va-arg-24.c zvl256b failure Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: norm

[Bug target/118036] [15 Regression] RISC-V: gcc.dg/vect/vect-alias-check-1[12].c abort

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118036 Edwin Lu changed: What|Removed |Added CC||rdapp at gcc dot gnu.org Summary|

[Bug target/118036] New: [15 Regression] RISC-V: gcc.dg/vect/vect-alias-check-11.c abort

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118036 Bug ID: 118036 Summary: [15 Regression] RISC-V: gcc.dg/vect/vect-alias-check-11.c abort Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/117970] [15 regression] RISC-V: xtreme-header failed to read compiled module: Bad file data

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117970 --- Comment #5 from Edwin Lu --- this testcase also appears to be flakey for these three targets: - rv32imac-ilp32d - rv64imac-lp64d - rv64imc_zicsr_zifencei-lp64d https://github.com/patrick-rivos/gcc-postcommit-ci/issues/2237 https://github.co

[Bug target/117991] New: [15] RISC-V: g++/template/builtin-speculation-overloads[14].C assertion error

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117991 Bug ID: 117991 Summary: [15] RISC-V: g++/template/builtin-speculation-overloads[14].C assertion error Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug target/117970] [15 regression] RISC-V: xtreme-header failed to read compiled module: Bad file data

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117970 --- Comment #4 from Edwin Lu --- (In reply to Lewis Hyatt from comment #2) > Thanks, I will see what I can find. Did you, by any chance, run the tests > before/after r15-6016 in the same build directory? I think this error would > make sense to

[Bug target/117970] [15 regression] RISC-V: xtreme-header failed to read compiled module: Bad file data

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117970 --- Comment #1 from Edwin Lu --- (In reply to Edwin Lu from comment #0) > Our postcommit ci is seeing the following regressions: > > FAIL: g++.dg/modules/xtreme-header-7_b.C -std=c++2b (test for excess errors) > FAIL: g++.dg/modules/xtreme-head

[Bug target/117970] New: [15 regression] RISC-V: xtreme-header failed to read compiled module: Bad file data

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117970 Bug ID: 117970 Summary: [15 regression] RISC-V: xtreme-header failed to read compiled module: Bad file data Product: gcc Version: 15.0 Status: UNCONFIRMED Seve

[Bug target/117906] New: [15 regression] RISC-V: gfortran.dg/sizeof_6.f90 -O1 timeout since r15-5897-g31250baf814

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117906 Bug ID: 117906 Summary: [15 regression] RISC-V: gfortran.dg/sizeof_6.f90 -O1 timeout since r15-5897-g31250baf814 Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug target/117771] [15 Regression] RISC-V: stage1 fails to build using gcc-9.4 since r15-5603-gb3f1b9e2aa0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117771 --- Comment #3 from Edwin Lu --- (In reply to Andrew Pinski from comment #2) > Created attachment 59699 [details] > Patch to test > > Can you test this patch? It moves the include of sstream above safe-ctype.h. > I don't know why it worked befo

[Bug target/117771] New: [9 Regression] RISC-V: stage1 fails to build using gcc-9.5 since r15-5603-gb3f1b9e2aa0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117771 Bug ID: 117771 Summary: [9 Regression] RISC-V: stage1 fails to build using gcc-9.5 since r15-5603-gb3f1b9e2aa0 Product: gcc Version: 9.5.0 Status: UNCONFIRMED

[Bug bootstrap/117407] [15 regression] bootstrap fails after r15-4847-g79a75b1f551821

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117407 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com --- Comment #2 from

[Bug libbacktrace/117413] [15 regression] RISC-V: stage2 build failure with __builtin_prefetch

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117413 Edwin Lu changed: What|Removed |Added Resolution|--- |DUPLICATE Status|UNCONFIRMED

[Bug libbacktrace/117413] New: [15 regression] RISC-V: stage2 build failure with __builtin_prefetch

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117413 Bug ID: 117413 Summary: [15 regression] RISC-V: stage2 build failure with __builtin_prefetch Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/114175] [13/14] Execution test failures on gcc.dg/c23-stdarg-6.c on multiple targets

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 Edwin Lu changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/116959] [15 regression] RISC-V: more ICEs in compute_nregs_for_mode

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116959 Edwin Lu changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/116822] [15 regression] RISC-V: ICE in compute_nregs_for_mode, at config/riscv/riscv-vector-costs.cc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116822 Edwin Lu changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug testsuite/117250] [15] RISC-V: gfortran.dg/unsigned_38.f90 Error: Operand of unary numeric operator '-' at (1) is UNSIGNED(4)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117250 Edwin Lu changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug testsuite/117250] New: [15] RISC-V: gfortran.dg/unsigned_38.f90 Error: Operand of unary numeric operator '-' at (1) is UNSIGNED(4)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117250 Bug ID: 117250 Summary: [15] RISC-V: gfortran.dg/unsigned_38.f90 Error: Operand of unary numeric operator '-' at (1) is UNSIGNED(4) Product: gcc Version: 15.0

[Bug target/117177] New: [15 regression] RISC-V: Error when building glibc from source since r15-4377-gf9bac238840

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117177 Bug ID: 117177 Summary: [15 regression] RISC-V: Error when building glibc from source since r15-4377-gf9bac238840 Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug tree-optimization/117140] [15 regression] RISC-V: ICE in initialize_flags_in_bb for rv32gcv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117140 --- Comment #3 from Edwin Lu --- Created attachment 59349 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=59349&action=edit reduced testcase (In reply to Andrew Pinski from comment #2) > I suspect r15-4324-gaccb85345edb91 . Confirmed to b

[Bug target/117140] New: [15 regression] RISC-V: ICE in initialize_flags_in_bb for rv32gcv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117140 Bug ID: 117140 Summary: [15 regression] RISC-V: ICE in initialize_flags_in_bb for rv32gcv Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/116959] [15 regression] RISC-V: more ICEs in compute_nregs_for_mode

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116959 --- Comment #1 from Edwin Lu --- Created attachment 59279 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=59279&action=edit vwsll-run.i

[Bug target/116959] New: [15 regression] RISC-V: more ICEs in compute_nregs_for_mode

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116959 Bug ID: 116959 Summary: [15 regression] RISC-V: more ICEs in compute_nregs_for_mode Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal P

[Bug target/116822] [15 regression] RISC-V: ICE in compute_nregs_for_mode, at config/riscv/riscv-vector-costs.cc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116822 Edwin Lu changed: What|Removed |Added CC||rguenth at gcc dot gnu.org --- Comment #2 fr

[Bug target/116822] [15 regression] RISC-V: ICE in compute_nregs_for_mode, at config/riscv/riscv-vector-costs.cc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116822 --- Comment #1 from Edwin Lu --- Bisected down to r15-3794-g2c04f175de4 as the first bad commit

[Bug target/116822] New: [15 regression] RISC-V: ICE in compute_nregs_for_mode, at config/riscv/riscv-vector-costs.cc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116822 Bug ID: 116822 Summary: [15 regression] RISC-V: ICE in compute_nregs_for_mode, at config/riscv/riscv-vector-costs.cc Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug tree-optimization/116820] [15 regression] RISC-V: ICE verify_ssa failed for c-c++-common/torture/pr101636.c since r15-3768-g4150bcd205e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116820 Edwin Lu changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/116820] [15 regression] RISC-V: ICE verify_ssa failed for c-c++-common/torture/pr101636.c since r15-3768-g4150bcd205e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116820 Edwin Lu changed: What|Removed |Added Summary|[15 regression] RISC-V: ICE |[15 regression] RISC-V: ICE

[Bug target/116686] [15 Regression] RISC-V: gcc.target/riscv/rvv/autovec/pr114734.c failing with zvl1024b lmul2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116686 --- Comment #5 from Edwin Lu --- Created attachment 59183 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=59183&action=edit tree output Here's the tree output

[Bug target/116686] [15 Regression] RISC-V: gcc.target/riscv/rvv/autovec/pr114734.c failing with zvl1024b lmul2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116686 --- Comment #4 from Edwin Lu --- Created attachment 59182 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=59182&action=edit verbose output Here's the verbose output

[Bug target/116820] New: [15 regression] RISC-V: ICE verify_ssa failed for c-c++-common/torture/pr101636.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116820 Bug ID: 116820 Summary: [15 regression] RISC-V: ICE verify_ssa failed for c-c++-common/torture/pr101636.c Product: gcc Version: 15.0 Status: UNCONFIRMED Severi

[Bug target/116686] New: [15 Regression] RISC-V: gcc.target/riscv/rvv/autovec/pr114734.c failing with zvl1024b lmul2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116686 Bug ID: 116686 Summary: [15 Regression] RISC-V: gcc.target/riscv/rvv/autovec/pr114734.c failing with zvl1024b lmul2 Product: gcc Version: 15.0 Status

[Bug target/116685] RISC-V: missed optimization on vector dot products

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116685 --- Comment #3 from Edwin Lu --- (In reply to Andrew Pinski from comment #1) > -fno-vect-cost-model fixes some of these. I hadn't taken a look with -fno-vect-cost-model until now but it seems like there's some weird codegen with the 3 element d

[Bug fortran/116661] Undefined behavior when compiling interop-1.f90 gomp test

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116661 --- Comment #5 from Edwin Lu --- (In reply to Thomas Schwinge from comment #4) > (In reply to GCC Commits from comment #3) > > commit r15-3581-g4e9265a474def98cb6cdb59c15fbcb7630ba330e > > Author: Tobias Burnus > > Date: Wed Sep 11 09:25:47 2

[Bug other/116685] New: RISC-V: missed optimization on vector dot products

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116685 Bug ID: 116685 Summary: RISC-V: missed optimization on vector dot products Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Componen

[Bug testsuite/116536] New: [15 Regression] gcc.dg/ipa/ipa-icf-38.c: error executing dg-final since r15-3254-g3f51f0dc88e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116536 Bug ID: 116536 Summary: [15 Regression] gcc.dg/ipa/ipa-icf-38.c: error executing dg-final since r15-3254-g3f51f0dc88e Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug libfortran/105361] Incorrect end-of-file condition for derived-type I/O

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105361 --- Comment #17 from Edwin Lu --- (In reply to Jerry DeLisle from comment #16) > Created attachment 58799 [details] > Revised test case with careful precision and tolerance values. > > New suggested test case which passes on x86-64-linux. We r

[Bug target/116425] New: RISC-V missed optimization: vector lowering along lmul boundaries

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116425 Bug ID: 116425 Summary: RISC-V missed optimization: vector lowering along lmul boundaries Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug rtl-optimization/115862] [15 Regression] RISC-V: ICE during RTL combine pass in malloc.c for zvl512b and zvl1024b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115862 Edwin Lu changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/116242] [meta-bug] Tracker for zvl issues in RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116242 Bug 116242 depends on bug 115862, which changed state. Bug 115862 Summary: [15 Regression] RISC-V: ICE during RTL combine pass in malloc.c for zvl512b and zvl1024b https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115862 What|Removed

[Bug target/116303] New: RISC-V: -mcpu doesn't populate .attribute arch string when directly invoking cc1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116303 Bug ID: 116303 Summary: RISC-V: -mcpu doesn't populate .attribute arch string when directly invoking cc1 Product: gcc Version: 15.0 Status: UNCONFIRMED Severit

[Bug target/116273] New: [14/15 regression] RISC-V: gcc.dg/long_branch.c flakey timeout

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116273 Bug ID: 116273 Summary: [14/15 regression] RISC-V: gcc.dg/long_branch.c flakey timeout Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/116261] New: [15 regression] RISC-V: gfortran.dg/sizeof_6.f90 -O1 timeout since r15-2739-g4cb07a38233

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116261 Bug ID: 116261 Summary: [15 regression] RISC-V: gfortran.dg/sizeof_6.f90 -O1 timeout since r15-2739-g4cb07a38233 Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug fortran/116255] New: [15 only] RISC-V: STOP 12 execution error on gfortran.dg/class_transformational_2.f90

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116255 Bug ID: 116255 Summary: [15 only] RISC-V: STOP 12 execution error on gfortran.dg/class_transformational_2.f90 Product: gcc Version: 15.0 Status: UNCONFIRMED Se

[Bug libstdc++/116247] New: [15] RISC-V: shared_ptr_atomic.h: uintptr_t not declared in scope

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116247 Bug ID: 116247 Summary: [15] RISC-V: shared_ptr_atomic.h: uintptr_t not declared in scope Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/113578] Incorrect sign printed for -nan on RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113578 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com --- Comment #12 fro

[Bug libfortran/105361] Incorrect end-of-file condition for derived-type I/O

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105361 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com --- Comment #10 fro

[Bug target/115862] New: [15] RISC-V: ICE during RTL combine pass in malloc.c for zvl512b and zvl1024b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115862 Bug ID: 115862 Summary: [15] RISC-V: ICE during RTL combine pass in malloc.c for zvl512b and zvl1024b Product: gcc Version: 15.0 Status: UNCONFIRMED Severity:

[Bug target/115741] New: [15] RISC-V: ICE in vectorizable_load, at tree-vect-stmts.cc:11524

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115741 Bug ID: 115741 Summary: [15] RISC-V: ICE in vectorizable_load, at tree-vect-stmts.cc:11524 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug tree-optimization/115387] [15 regression] RISC-V: ICE in iovsprintf.c since r15-1081-ge14afbe2d1c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115387 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com,

[Bug target/115387] New: [15] RISC-V: ICE in iovsprintf.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115387 Bug ID: 115387 Summary: [15] RISC-V: ICE in iovsprintf.c Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug tree-optimization/115220] [15 Regression] RISC-V: newlib targets ICE during sink pass triggered in verify_ssa

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115220 --- Comment #3 from Edwin Lu --- (In reply to Andrew Pinski from comment #1) > Can you provide the preprocessed source? I attached the -freport-bug output. Please lmk if you need anything else!

[Bug tree-optimization/115220] [15 Regression] RISC-V: newlib targets ICE during sink pass triggered in verify_ssa

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115220 --- Comment #2 from Edwin Lu --- Created attachment 58283 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58283&action=edit -freport-bug output

[Bug target/115220] New: [15] RISC-V: newlib targets ICE during sink pass triggered in verify_ssa

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115220 Bug ID: 115220 Summary: [15] RISC-V: newlib targets ICE during sink pass triggered in verify_ssa Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: norma

[Bug testsuite/115166] New: RISC-V: flakey relocation truncated to fit: R_RISCV_GPREL_I against `.LANCHOR1' in slp_run-2.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115166 Bug ID: 115166 Summary: RISC-V: flakey relocation truncated to fit: R_RISCV_GPREL_I against `.LANCHOR1' in slp_run-2.c Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug target/115142] [14/15 Regression] Unrecognizable insn in extract_insn, at recog.cc:2812 with -ftree-ter

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115142 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com --- Comment #1 from

[Bug lto/114662] [14 regression] new test case c_lto_pr113359-2 from r14-9841-g1e3312a25a7b34 fails

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114662 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com,

[Bug rtl-optimization/114515] [14 Regression] Failure to use aarch64 lane forms after PR101523

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114515 --- Comment #8 from Edwin Lu --- (In reply to Robin Dapp from comment #7) > There is some riscv fallout as well. Edwin has the details. I haven't done an in depth analysis but the full list of new riscv scan-dump failures can be found here: ht

[Bug target/114175] [13/14] Execution test failures on gcc.dg/c23-stdarg-6.c on multiple targets

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 --- Comment #32 from Edwin Lu --- riscv patch: https://gcc.gnu.org/pipermail/gcc-patches/2024-March/647963.html tested with rv64gcv-lp64d. waiting on precommit testing results

[Bug tree-optimization/113281] [11/12/13 Regression] Latent wrong code due to vectorization of shift reduction and missing promotions since r9-1590

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113281 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com --- Comment #25 fro

[Bug target/114175] [13/14] RISC-V: Execution test failures on gcc.dg/c23-stdarg-6.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 --- Comment #19 from Edwin Lu --- While debugging, I found that this testcase also breaks on x86_64 when optimizations are enabled (-O1 -> -O3). Godbolt: https://godbolt.org/z/ecs5MPds8 There may be other targets that fail as well. I haven't

[Bug middle-end/114197] [14] middle-end: ICE in verify_dominators

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114197 --- Comment #3 from Edwin Lu --- Patch: https://gcc.gnu.org/pipermail/gcc-patches/2024-March/647031.html

[Bug middle-end/114197] [14] middle-end: ICE in verify_dominators

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114197 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com,

[Bug middle-end/114197] New: [14] middle-end: ICE in verify_dominators

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114197 Bug ID: 114197 Summary: [14] middle-end: ICE in verify_dominators Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: middle

[Bug target/114175] [13/14] RISC-V: Execution test failures on gcc.dg/c23-stdarg-6.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 --- Comment #16 from Edwin Lu --- (In reply to palmer from comment #15) > It's a little easier to see from the float version of the code. > > $ cat gcc/testsuite/gcc.dg/c23-stdarg-6.c > /* Test C23 variadic functions with no named parameters,

[Bug target/114175] [14] RISC-V: Execution test failures on gcc.dg/c23-stdarg-6.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 --- Comment #4 from Edwin Lu --- (In reply to Jakub Jelinek from comment #3) > (In reply to Edwin Lu from comment #2) > > Applied the patch on top of r14-9243-g02ca9d3f0c5. Looks like the problem is > > still there. > > - else if (TYPE_NO_NAMED

[Bug target/114175] [14] RISC-V: Execution test failures on gcc.dg/c23-stdarg-6.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 --- Comment #2 from Edwin Lu --- (In reply to Jakub Jelinek from comment #1) > Does the > https://gcc.gnu.org/pipermail/gcc-patches/2024-February/646882.html > patch fix that? > The test was committed ahead exactly to find out what targets have

[Bug target/114175] New: [14] RISC-V: Execution tests on gcc.dg/c23-stdarg-6.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114175 Bug ID: 114175 Summary: [14] RISC-V: Execution tests on gcc.dg/c23-stdarg-6.c Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Compo

[Bug target/114122] New: RISC-V: poor code generation in calling convention with vlen > 4096

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114122 Bug ID: 114122 Summary: RISC-V: poor code generation in calling convention with vlen > 4096 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug target/113913] New: [14] RISC-V: suboptimal code gen for intrinsic vcreate

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113913 Bug ID: 113913 Summary: [14] RISC-V: suboptimal code gen for intrinsic vcreate Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Comp

[Bug c++/113710] [14 Regression] g++.dg/modules/hello-1 ICE: canonical types differ for identical types since r14-8710-g65b4cba9d6a9ff

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113710 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com,

[Bug target/113035] RISC-V: -mtune=sifive-7-series additional dump failures found with bitmanip, zicond, and vector targets

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113035 --- Comment #1 from Edwin Lu --- Created attachment 57106 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=57106&action=edit testsuite failures for rv64 bitmanip and vector as of r14-7474-g7d8de1ca4a7 Double checked for execution failures o

[Bug target/113249] RISC-V: regression testsuite errors -mtune=generic-ooo

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113249 --- Comment #3 from Edwin Lu --- (In reply to Edwin Lu from comment #2) > > If there are new execution failures that would be more concerning and > > indicate a real bug. > I've gone through a few of the differences between rocket and generic-oo

[Bug target/113249] RISC-V: regression testsuite errors -mtune=generic-ooo

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113249 --- Comment #2 from Edwin Lu --- (In reply to Robin Dapp from comment #1) > Yes, several (most?) of those are expected because the tests rely on the > default latency model. One option is to hard code the tune in those tests. > On the other han

[Bug target/113248] RISC-V: Invalid vsetvli fusion using -mtune=generic-ooo

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113248 Edwin Lu changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/113249] New: RISC-V: regression testsuite errors -mtune=generic-ooo

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113249 Bug ID: 113249 Summary: RISC-V: regression testsuite errors -mtune=generic-ooo Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Comp

[Bug target/113248] New: RISC-V: Invalid vsetvli fusion using -mtune=generic-ooo

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113248 Bug ID: 113248 Summary: RISC-V: Invalid vsetvli fusion using -mtune=generic-ooo Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Prior

[Bug testsuite/113238] [14] RISC-V: gcc.dg vect-tsvc flakey test timeouts when under heavy workload

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113238 --- Comment #1 from Edwin Lu --- Debug log for one of the flakey tests spawn -ignore SIGHUP /github/patrick-postcommit-runner-2/_work/gcc-postcommit-ci/gcc-postcommit-ci/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc -B/github/patric

[Bug testsuite/113238] New: [14] RISC-V: gcc.dg vect-tsvc flakey test timeouts when under heavy workload

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113238 Bug ID: 113238 Summary: [14] RISC-V: gcc.dg vect-tsvc flakey test timeouts when under heavy workload Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: n

[Bug target/113076] [14] RISC-V: gfortran.dg/dec_io_1.f90 runtime error after r14-4972-g8aa47713701

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113076 Edwin Lu changed: What|Removed |Added Summary|[14] RISC-V:|[14] RISC-V: |gfortran.dg/

[Bug target/113076] New: [14] RISC-V: gfortran.dg/dec_io_1.f90 runtime error after r14-4971-g0beb1611754

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113076 Bug ID: 113076 Summary: [14] RISC-V: gfortran.dg/dec_io_1.f90 runtime error after r14-4971-g0beb1611754 Product: gcc Version: 14.0 Status: UNCONFIRMED Severity

[Bug target/113073] New: [14] RISC-V: segfault from out of bounds memory access in gcc.dg/torture/pr112736.c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113073 Bug ID: 113073 Summary: [14] RISC-V: segfault from out of bounds memory access in gcc.dg/torture/pr112736.c Product: gcc Version: 14.0 Status: UNCONFIRMED Seve

[Bug target/112896] RISC-V: gcc.dg/pr30957-1.c run failure when rv64gcv_zvl1024b_zvfh_zfh

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112896 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com --- Comment #1 from

[Bug target/113009] [14] RISC-V: gcc.c-torture/unsorted/dump-noaddr.c flakey tests

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113009 Edwin Lu changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/113035] New: RISC-V: -mtune=sifive-7-series additional dump failures found with bitmanip, zicond, and vector targets

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113035 Bug ID: 113035 Summary: RISC-V: -mtune=sifive-7-series additional dump failures found with bitmanip, zicond, and vector targets Product: gcc Version: 14.0

[Bug target/113009] [14] RISC-V: gcc.c-torture/unsorted/dump-noaddr.c flakey tests

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113009 --- Comment #4 from Edwin Lu --- (In reply to JuzheZhong from comment #3) > (In reply to Edwin Lu from comment #2) > > Re-bisected to r14-6197-g2e7abd09621 > > > > Full steps to reproduce: > > mkdir dump1 > > ./build-gcc-linux-stage2/gcc/xgcc -

[Bug target/113009] [14] RISC-V: gcc.c-torture/unsorted/dump-noaddr.c flakey tests

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113009 Edwin Lu changed: What|Removed |Added CC||juzhe.zhong at rivai dot ai --- Comment #2 f

[Bug target/113009] [14] RISC-V: gcc.c-torture/unsorted/dump-noaddr.c flakey tests

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113009 --- Comment #1 from Edwin Lu --- Found issue with bisection script. Currently re-bisecting

[Bug target/113009] New: [14] RISC-V: gcc.c-torture/unsorted/dump-noaddr.c flakey tests

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113009 Bug ID: 113009 Summary: [14] RISC-V: gcc.c-torture/unsorted/dump-noaddr.c flakey tests Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal

[Bug target/112531] [14] RISC-V: gcc.dg/unroll-8.c rtl-dump scan errors with --param=riscv-autovec-preference=scalable

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112531 --- Comment #3 from Edwin Lu --- (In reply to JuzheZhong from comment #1) > This FAIL is reasonable. So we can ignore it. > > The vectorized code will fail at this dump check like ARM SVE: > https://godbolt.org/z/dbsKb7bxY > > Or you can fix t

[Bug target/111311] RISC-V regression testsuite errors with --param=riscv-autovec-preference=scalable

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111311 Edwin Lu changed: What|Removed |Added CC||ewlu at rivosinc dot com --- Comment #17 fro

[Bug target/112531] New: [14] RISC-V: gcc.dg/unroll-8.c rtl-dump scan errors with --param=riscv-autovec-preference=scalable

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112531 Bug ID: 112531 Summary: [14] RISC-V: gcc.dg/unroll-8.c rtl-dump scan errors with --param=riscv-autovec-preference=scalable Product: gcc Version: 14.0 Status: UNCONFIRMED

[Bug c++/108321] [13 regression] g++.dg/contracts/contracts-tmpl-spec2.C fails after r13-4160-g2efb237ffc68ec

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108321 --- Comment #5 from Edwin Lu --- (In reply to seurer from comment #3) This also appears in GCC 14 for riscv64 targets with the same output pattern above. After a quick comparison with the expected output, this output is missing > contract viol

[Bug target/111545] [14 Regression] RISC-V gfortran.dg/host_assoc_function_7.f09 Illegal instruction error

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111545 Edwin Lu changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

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