, which causes crash.
So I am forced to remove the -mfpu=neon for compatibility. My
question is whether the gcc code show above confront to ARM
standard. If so, why ARM make such a weird standard.
--
Lin Zuojian
? Let's take
a look at this.
--
Lin Zuojian
Hi,
I knew what is going on now. strict_aliasing_warning has not
considered tbaa. We might want to fix it.
--
Lin Zuojian
Hi,
record_component_aliases only handle fields of a record type, and
would ignore the base of this record if the base has no field
declaration.
Is this a bug or on purpose?
Thanks.
--
Lin Zuojian
Thanks Richard.
---
Lin Zuojian
forest| | push.. |
| | ||
-- --
--
Lin Zuojian
+ e->src->total_wight < e.dest->total_wight)
{
e->dest.total_wight = e->wight + e->src->total_wight;
e->dest.parent = e->src;
}
}
I think it's really O(n) for a dfs right?
That's what I want to proposed.
--
Lin Zuojian
done after lra elimiation, inheriation, ...
Any professional can help me out? Thanks.
---
Lin Zuojian
wrote:
> On 09/12/14 20:37, lin zuojian wrote:
> > Hi,
> > I have read ira/lra code for a while, but still fails to understand
> > their relationship. The main question is why ira do color so early?
> > lra pass will do the assignment anyway. Sorry if I mess u
Moreover, LRA assignment does not refer to the assignment result of ira
directly. In find_hard_regno_for, the value of hard_regno comes from
ira_class_hard_regs[rclass][i] with least cost.
On Tue, Dec 09, 2014 at 06:14:29PM +0800, lin zuojian wrote:
> Hi Kugan,
> I have read these pd
Thanks Vladimir & Jeff & Kugan. Combining the replies I get a better
view of RA problem.
--
Lin Zuojian
On Tue, Dec 09, 2014 at 12:10:29PM -0500, Vladimir Makarov wrote:
> On 12/09/2014 04:37 AM, lin zuojian wrote:
> > Hi,
> > I have read ira/lra code for a while, but st
LLVM/clang:
real0m32.036s
user0m32.001s
sys 0m0.000s
That mean movabsq did do a better job!
Should gcc peephole pass add such a combine?
--
Regards
lin zuojian
Hi guys,
How do I set the format of vim,so that my code doen't look alien?
--
Regards
lin zuojian
Thx,Jonathan.
--
Regards
lin zuojian
On Mon, Mar 03, 2014 at 09:37:01AM +, Jonathan Wakely wrote:
> On 3 March 2014 07:00, lin zuojian wrote:
> > Hi guys,
> > How do I set the format of vim,so that my code doen't look alien?
>
> Do you mean how do you set v
on without "volatile" key word?
--
Regards
lin zuojian
s a barrier.
> >
> > Sure. My question was about the volatile marker. asm("":::"memory") should
> > act
> > as the barrier alone.
>
> __asm__("":::"memory")
>
> is a memory barrier
>
> volatile __asm__("":::"memory")
>
> is a memory barrier and a barrier for other volatile instructions.
Hi Andrew,
What is volatile instructions?Can you give us an example?
--
Regards
lin zuojian
e same cfa offset when coming to the
joint.
--
Regards
lin zuojian
ing first,and then cfa 96.
Anybody has any comment to fix it?
--
Regards
lin zuojian
On Wed, Mar 05, 2014 at 10:39:51AM +0400, Yury Gribov wrote:
> >What is volatile instructions? Can you give us an example?
>
> Check volatile_insn_p. AFAIK there are two classes of volatile instructions:
> * volatile asm
> * unspec volatiles (target-specific instructions for e.g. protecting
> func
LLVM can not do sched2.Is that
suck?
--
Regards
lin zuojian.
On Mon, Mar 10, 2014 at 07:11:43PM -0700, Chandler Carruth wrote:
> On Mon, Mar 10, 2014 at 6:59 PM, lin zuojian wrote:
> >
> > Hi,
> > I read LLVM code for a while,and a question raise:Whose scheduler is
> > better?
> > LLVM brings in the DAG,and ma
Hi Chandler,
Thanks a lot for your answer.It is pretty misleading to find out
that DAG has schedule unit.
--
Regards
lin zuojian
On Tue, Mar 11, 2014 at 11:30:28AM +0800, lin zuojian wrote:
> Hi Chandler,
> Thanks a lot for your answer.It is pretty misleading to find out
> that DAG has schedule unit.
> --
> Regards
> lin zuojian
Hi Chandler,
I have looked into their "Machine Instr S
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