From tree dump we can see that there are two assignments from x, one
to unsigned and one to signed. I guess that's the reason. Apparently
there is room to improve though.
int prephitmp.8;
int * D.2027;
unsigned int D.2026;
unsigned int x.1;
int x.0;
# BLOCK 2 freq:1
# PRED: ENTR
On Wed, Nov 30, 2011 at 7:53 AM, Han Shen(沈涵) wrote:
> Hi, I propose to add to gcc a new option regarding stack protector -
> "-fstack-protector-strong", in addition to current gcc's
> "-fstack-protector-all", which protects ALL functions, and
> "-fstack-protector", which protects functions that h
On Thu, Dec 22, 2011 at 12:43 AM, Ian Lance Taylor wrote:
> Terry Guo writes:
>
>> I plan to set up daily regression test on trunk for target
>> ARM-NONE-EABI and post results to gcc-testresults mailing list. Which
>> Binutils should I use, the Binutils trunk or the latest released
>> Binutils? A
袁立威 wrote:
> Hi, I'm a guy working with gcc4.1.1 on itanium2. In my work, some
> instrumentations are added by gcc. After instrumentation, all
> specint2000 benchmarks except gzip can successfully run with
> optimization flag -O3. There are some information list below:
No answer from me but hopeful
Maybe comments at the insn pattern who emit "rep\; ret" can explain it:
";; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
;; instruction Athlon and K8 have."
Thanks - Joey
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Etienne
When I write schedule model for following instructions:
Insn1: mov %r1, %r2
Insn2: mov %r1, %r3
Insn3: foo %r2, %r3 (foo is a 3 op insn, for example, %r3 = %r3 << %r2)
Latency from insn1 to insn3 is x cycles, and latency from insn2 to insn3 is y
cycles. x != y.
Both insn1 and insn2 are insn_res
Maxim and Vladimir Wrote:
>>> Anyone can help me through this please?
>>>
>> It was supposed to have two latency definitions at most (one in
>> define_insn_reservation and another one in define_bypass). That time it
>> seemed enough for all processors supported by GCC. It also simplified
>>
Maxim and Vladimir Wrote:
>>> Anyone can help me through this please?
>>>
>> It was supposed to have two latency definitions at most (one in
>> define_insn_reservation and another one in define_bypass). That time it
>> seemed enough for all processors supported by GCC. It also simplified
>>
Vladimir Makarov [mailto:vmaka...@redhat.com] wrote:
> It was supposed to have two latency definitions at most (one in
> define_insn_reservation and another one in define_bypass). That time it
> seemed enough for all processors supported by GCC. It also simplified
> semantics definition when t
Maxim Kuvyrkov [mailto:ma...@codesourcery.com] wrote:
> Yes, it does depend on this assumption and the comment states exactly that.
What I concerned is that the assumption may be broken someday, unless scheduler
guarantees it.
> Which check[s] do you have in mind, the gcc_assert's? Also, out of
This is about http://gcc.gnu.org/bugzilla/show_bug.cgi?id=38736 and I'd rather
discuss it in gcc mail list. Basicly the problem is shown as following example:
Case 1 (on x86 or x86_64):
$ cat i.h
struct s
{
char dummy0;
// align at maxmiun aligned boundary supported by this target.
ch
From: Ian Lance Taylor [mailto:i...@google.com]:
> Therefore, I propose that we do the following:
>
> 1) Introduce __attribute__ ((aligned (scalar))). This will be
>documented as having a fixed value for each ABI. The value will be
>guaranteed to be sufficient to hold any ordinary non-ve
In following example, call to sbfoo isn't a tail call with -O2. GCC
analyzes local variable may be referenced in sbfoo. Is it a reasonable
analysis? In another word, is it a legal program that bar stores
address of local to a static variable, and then for sbfoo to access
it?
This issue cause a mis
On Fri, Jan 11, 2013 at 2:29 AM, Louis-Philippe Brais
wrote:
> Hi all,
>
> The latest errata for Texas Instruments' Cortex-M3 family, updated
> last October [1], contains a disturbing new problem triggered by
> non-word-aligned writes to SRAM. This is the kind of errata that is
> effectively addre
Following case attempts to set floating point control register and
execute floating point operation afterward. However, it doesn't works
as expected with -Os, as GCC hoists multiply operation beyond FP
control register setting.
As there is no register dependence between __set_FPSCR and multiply,
h
On Wed, 13 Feb 2008, H.J. Lu wrote:
>> Recent i386 use arbitrary register as GOT pointer only for leaf
>> function. When you call something, the GOT entry uses EBX too.
>> We use RBX for large PIC model. But I am with Michael here that I
don't
>> see reason why choice of register needs to be
Honza,
> Honza said:
> I am bit confused here. If I wanted a free register in prologue only,
I
> would probably look at the caller saved ones. But I gues it is just
> typo.
> I don't see much value in making the register callee-saved especially
if
> you say that virtual reg (pseudo?) is used af
Ross, Christian,
Here are the patches to implement the idea we discussed before. Can you
take a look at it or try it?
http://gcc.gnu.org/ml/gcc-patches/2008-03/msg01200.html
http://gcc.gnu.org/ml/gcc-patches/2008-03/msg01199.html
Thanks - Joey
Hi,
From i386.md, alternative 1 of *fop_sf_comm_mixed is duplicated with
*fop_sf_comm_sse. Why do we define a _mixed pattern here?
(define_insn "*fop_sf_comm_mixed"
[(set (match_operand:SF 0 "register_operand" "=f,x")
(match_operator:SF 3 "binary_fp_operator"
[(m
I got following error after changing some GCC code, can anyone give me
some hints what's wrong here?
---
error: insn does not satisfy its constraints:
(insn:HI 690 689 1267 79 libgcc/config/libbid/bid_binarydecimal.c:146450
(parallel [
(set (mem/c:DI (plus:SI (reg:SI 2 cx [59])
Daniel,
We generate following DWARF2 instructions for stack alignment prologue.
Basically we use expression to calculate CFA. But it run into some
segfault in libmudflap and libjava. Do you have any hints what's wrong?
DW_CFA_def_cfa: r4 (esp) ofs 4
DW_CFA_offset: r8 (eip) at cfa-4
DW_CFA_n
, 2008 10:00 PM
To: H.J. Lu
Cc: Ye, Joey; gcc@gcc.gnu.org; Guo, Xuepeng
Subject: Re: CFA expression failure
On Tue, Jun 24, 2008 at 08:40:18PM -0700, H.J. Lu wrote:
> I think the problem is in uw_update_context_1. REG_SAVED_EXP
> and REG_SAVED_VAL_EXP may use other registers as shown
4.3 trunk revision 126185 I got at x86_64:
libtool: compile: unable to infer tagged configuration
libtool: compile: specify a tag with `--tag'
make[6]: *** [kill.lo] Error 1
Anyone else got the same?
126184 passes. Looks like problems in this check:
r126185 | kargl | 2007-07-02 10:47:21 +0800 (M
Matt,
I just started working on pipeline description and I'm confused one thing in
your description.
For "integer", your cpu have a 1-cycle latency, but with 3 units stages
"issue,iu,wb". What does that mean? My understanding is that the number of
units seperated by "," should be equal to late
I like option B. It will be very helpful to reduce software product development
time. Some software product just release with -O0 because they are not
confident releasing a version differ to the one they were debugging and testing
in.
Also in some systems -O0 simply doesn't work, which is too
-- 0. MOTIVATION --
Some local variables (such as of __m128 type or marked with alignment
attribute) require stack aligned at a boundary larger than the default
stack
boundary. Current GCC partially supports this with limitations. We are
proposing a new design to fully solve the problem.
-- 1. CU
inal Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of H.J. Lu
Sent: 2007年12月18日 13:17
To: Ross Ridge
Cc: gcc@gcc.gnu.org
Subject: Re: A proposal to align GCC stack
On Mon, Dec 17, 2007 at 11:25:35PM -0500, Ross Ridge wrote:
> Ye, Joey writes:
> >i. STACK_BOUNDAR
Ross Ridge wrote:
> I'm currently using -fpreferred-stack-boundary without any trouble.
> Your proposal would in fact generate code to align stack when it's not
> necessary. This would change the behaviour of
-fpreferred-stack-boundary,
> hurting performance and that's unacceptable to me.
This p
Thanks for Ross and HJ's comments. Here is updated proposal:
Changes:
- value of REQUIRED_STACK_BOUNDARY of leaf function
- value of INCOMING_STACK_BOUNDARY
-- 0. MOTIVATION --
Some local variables (such as of __m128 type or marked with alignment
attribute) require stack aligned at a boundary la
Ye, Joey writes:
>> This proposal values correctness at first place. So when compile
can't
>> make sure a function is only called from functions with the same or
bigger
>> preferred-stack-boundary, it will conservatively align the stack. One
>> optimization is to set I
Andrew,
My proposal is supposed not limited to i386/x86_64. Would do please
spend some time review it and see if it can really solve problem in PowerPC?
Your comments is welcome.
Thanks - Joey
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Andrew Pins
Christian Schüler writes:
> Please go forward with this idea!
> The current implementation of force_align_arg_pointer has never worked for me.
This proposal should solve your problem. But to comfirm, I'd like to know the
root cause. force_align_arg_pointer should have guaranteed 16 bytes align.
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