Hello everyone,
As a proof of concept, I am trying to extend the gcc spu backend to produce
a few new assembly instructions, specifically loads and stores of the form
Load rt, s2(s18)
Store s2(s18), rc
However after searching and reading a lot of documentation, I still cannot
figure out all the
I basically need to test the retarget ability of named address spaces, and
it was determined that the best way to do this was to attempt to have the
SPU implementation spit out a few assembly mnemonics that resemble what our
architecture uses to handle multiple address spaces(hence the loads and
s
Hello all,
While prototyping a port of gcc I think that the RTX is lacking some
information needed to generate machine dependent files. The expression
trees have the correct information and I can likely hack in a quick fix to
pass that information down to the backend. However, I just want to make
Hello Everyone,
I am working on an architecture with multiple types of memory and I am
wondering about memory allocation. For the purpose of this explaination,
we'll assume I am working with an embedded processor that has both 32 bit
(named X) and 64 bit memory (named Y), 64 bit longs, and uses w
