Hi,
I'd like to make a backend which would have 48 bits for 'long' type.
(32 for int and 64 for long long).
I have tried to define:
#define LONG_TYPE_SIZE 48
and one of:
INT_MODE (PDI, 6);
PARTIAL_INT_MODE (DI);
Unfortunately, trying to compile a program, I see that the backend
still uses SImo
On Mon, Mar 8, 2010 at 8:29 AM, Joern Rennecke
wrote:
> Quoting Frank Isamov :
>
>> Hi,
>>
>> I'd like to make a backend which would have 48 bits for 'long' type.
>> (32 for int and 64 for long long).
>>
>> I have tried to define:
>&
On Mon, Mar 8, 2010 at 4:27 PM, Frank Isamov wrote:
> On Mon, Mar 8, 2010 at 8:29 AM, Joern Rennecke
> wrote:
>> Quoting Frank Isamov :
>>
>>> Hi,
>>>
>>> I'd like to make a backend which would have 48 bits for 'long' type.
>>&
We have a problem with arguments passing in memory.
The caller puts the arguments in memory relative to the sp:
add sp, 4 // allocate space for the argument. stack grows up
store r1, (sp-4) // store the argument on the stack
call xxx// call the function.
In xxx the result co
Hi,
In my backend, I have a problem with the pass which determines the
best register class for a virtual register (Pass 0 for finding allocno
costs).
In all insns in this example both R_REGS and D_REGS register classes
are applicable (but all registers in an insn should be from the same
register
-- Forwarded message --
From: Frank Isamov
Date: Thu, Mar 18, 2010 at 4:28 PM
Subject: Re: Coloring problem - Pass 0 for finding allocno costs
To: Ian Bolton
On Thu, Mar 18, 2010 at 3:51 PM, Ian Bolton wrote:
>> The problem I see is that for registers 100,101 I ge
Hi,
My architecture supports instructions with two parallel side effects.
For example, addition and subtraction can be done in parallel:
(define_insn "assi6"
[(parallel [
(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 1 "register_operand" "r")
On Mon, Apr 19, 2010 at 5:54 PM, Jeff Law wrote:
>
> combine requires a data dependency, so for this situation, combine isn't
> going to help. The easy solution is to create a peephole. You can also
> create a machine dependent reorg pass to detect more of these opportunities.
> Jeff
>
Hi
Hi Ian,
On Wed, Apr 21, 2010 at 5:42 PM, Ian Lance Taylor wrote:
> Frank Isamov writes:
>
>> 2. A peephole for such case just repeats instruction definition
>> pattern. As all information already available for such peephole,
>> wouldn’t it be useful to implement the
