---------- Forwarded message ----------
From: Frank Isamov <frank.isa...@gmail.com>
Date: Thu, Mar 18, 2010 at 4:28 PM
Subject: Re: Coloring problem - Pass 0 for finding allocno costs
To: Ian Bolton <bol...@icerasemi.com>
On Thu, Mar 18, 2010 at 3:51 PM, Ian Bolton <bol...@icerasemi.com> wrote:
>> The problem I see is that for registers 100,101 I get best register
>> class D instead of R - actually they get the same cost and D is chosen
>> (maybe because it is first).
>
> Hi Frank.
>
> Do D and R overlap? It would be useful to know which regs are in
> which class, before trying to understand what is going on.
>
> Can you paste an example of your define_insn from your MD file to show
> how operands from D or R are both valid? I ask this because it is
> possible to express that D is more expensive than R with operand
> constraints.
>
> For general IRA info, you might like to look over my long thread on
> here called "Understanding IRA".
>
> Cheers,
> Ian
>
Hi Ian,
Thank you very much for your prompt reply.
D and R are not overlap. Please see fragments of .md and .h files below:
From the md:
(define_register_constraint "a" "R_REGS" "")
(define_register_constraint "d" "D_REGS" "")
(define_predicate "a_operand"
(match_operand 0 "register_operand")
{
unsigned int regno;
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
regno = REGNO (op);
return (regno >= FIRST_PSEUDO_REGISTER ||
REGNO_REG_CLASS(regno) == R_REGS);
}
)
(define_predicate "d_operand"
(match_operand 0 "register_operand")
{
unsigned int regno;
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
regno = REGNO (op);
return (regno >= FIRST_PSEUDO_REGISTER ||
REGNO_REG_CLASS(regno) == D_REGS);
}
)
(define_predicate "a_d_operand"
(ior (match_operand 0 "a_operand")
(match_operand 0 "d_operand")))
(define_predicate "i_a_d_operand"
(ior (match_operand 0 "immediate_operand")
(match_operand 0 "a_d_operand")))
(define_insn "mov<mode>_regs"
[(set (match_operand:SISFM 0 "a_d_operand" "=a, a, a, d, d, d")
(match_operand:SISFM 1 "i_a_d_operand" "a, i, d, a, i, d"))]
""
"move\t%1, %0"
)
(define_insn "*addsi3_1"
[(set (match_operand:SI 0 "a_d_operand" "=a, a, a,d,d")
(plus:SI (match_operand:SI 1 "a_d_operand" "%a, a, a,d,d")
(match_operand:SI 2 "nonmemory_operand"
"U05,S16,a,d,U05")))]
""
"adda\t%2, %1, %0"
)
;; Arithmetic Left and Right Shift Instructions
(define_insn "<shPat><mode>3"
[(set (match_operand:SCIM 0 "register_operand" "=a,d,d")
(sh_oprnd:SCIM (match_operand:SCIM 1 "register_operand" "a,d,d")
(match_operand:SI 2
"nonmemory_operand" "U05,d,U05")))
(clobber (reg:CC CC_REGNUM))]
""
"<shIsa>\t%2, %1, %0"
)
From the h file:
#define REG_CLASS_CONTENTS \
{
\
{0x00000000, 0x00000000, 0x00000000}, /* NO_REGS*/ \
{0xFFFFFFFF, 0x0000FFFF, 0x00000000}, /* D_REGS*/ \
{0x00000000, 0xFFFF0000, 0x0000FFFF}, /* R_REGS*/ \
ABI requires use of R registers for arguments and return value. Other
than that all of these instructions are more or less symmetrical in
sense of using D or R. So, an optimal choice would be use of R for
this example. And if D register is chosen, it involves additional copy
from R to D and back to R.
Thank you, Frank
