ardware interlocks in the
gcc mailing list
which is dated in 2007. (https://gcc.gnu.org/ml/gcc/2007-07/msg00915.html)
Is it still true?
Thanks,
David.
--
------
Dr. Dong-In "David" Kang
Computer Scientist
USC/ISI
r
operands[0] across those three instructions.
Is it possible?
Or would there be any better way to generate efficient FPU code?
I will appreciate any advice or pointer to further information.
Thanks,
David
--
--
Dr. Dong-In "David" Kang
Computer Scientist
USC/ISI
---
> From: "Jeff Law"
> To: "David Kang" , gcc@gcc.gnu.org
> Sent: Monday, November 3, 2014 11:21:58 AM
> Subject: Re: how to keep a hard register across multiple instrutions?
> On 10/31/14 16:01, David Kang wrote:
> >
> > Hi,
> >
> >
Thank you very much.
It turns out that the FPU register is renamed.
After configuring HARD_REGNO_RENAME_OK, now one FPU register is used for those
three instructions.
David
- Original Message -
> From: "Joern Rennecke"
> To: "David Kang"
> Cc: "
d someone tell me what I am doing wrong?
And I'll appreciate what architecture is similar and helpful for me to port gcc
with the newly added FPU.
Thanks,
David
--
--
Dr. Dong-In "David" Kang
Computer Scientist
USC/ISI
.
But none of them work.
(define_expand "seqf2"
[(set (match_operand:SI 0 "register_operand" "")
(eq:SI (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "register_operand" "")))]
-
> From: "Segher Boessenkool"
> To: "David Kang"
> Cc: "GCC"
> Sent: Tuesday, November 25, 2014 3:25:47 PM
> Subject: Re: optab handler for floating point to interger "fix" is not
> generated
> On Tue, Nov 25, 2014 at 10:4
