Hi,
According to me at this moment the scheduler does not support your needs.
I was confronted with a similar problem as yours and I solved it by
implementing the TARGET_SCHED_DFA_NEW_CYCLE hook. Inside of the function which
supports this hook I choose/set the insn reservation that makes possib
> Gcc only does this work in the second pass, but what's the
> point? Is it wrong or just not necessary in the first sched
> pass?
Regardless of the target architecture from the correctness point of view sched1
can be disabled. sched1 has as purpose shortening live ranges.
Short live ranges allo
> With 4.4, IRA happens to reuse the same register for both pseudos, so
> sched2 is hand tied and cannot schedule them back again for us.
I can imagine compiling other programs for which preserving the 4.3 allocation
will induce performance degradation due to spilling.
The register allocator t
Dear all,
Im writing to you regarding the dead store elimination (dse) which runs after
register allocation. Apparently dse removes wrongly the following store
(present in bb2):
(insn 374 47 52 2 test.c:107 (set (mem/c:SI (plus:PSI (reg/f:PSI 55 ptr15)
(const_int 96 [0x60])) [19
Hi Michael,
> My assumption would be these two split loads of HImode are
> generated by your backend from a given SImode MEM.
Indeed your asumption is right. Bellow I have a mulsi3 expand in which I
generate insns of mode HI. operands[1] gets spilled: in the produced BB as a
single SI store wh
Im writing to you regarding a possible bug in linear loop transfor.
The bug can be reproduce by compiling the attached c file with gcc.4.5.0
(20100204, 20100325) on x86 machine.
The compiler flags that reproduce the error are:
-O2 -fno-inline -fno-tree-ch -ftree-loop-linear
If the compiler is ru
Hi all,
Im building a gcc target for a vliw machine that can execute the same
instruction on different resources (slots) and depending on which resources are
allocate the instruction must have a different mnemonic. Is it possible in gcc
to have for the same define_insn constraints (depending on
return "add-slot1, %0, %1, %2";
> }
> }
> [(set_attr "type" "alu")
>(set_attr "mode" "SI")
>(set_attr "length" "1")])
>
> > -Original Message-
> > From: [EMAIL PROTECT
> Keep
> track of the instruction slot, and set some global variable
> in that macro.
I see what you mean but for my target architecture the slots are not
identical in sense that they are claiming totaly different resources.
This means that in order to decide at a certain cycle which mnemonic
Dear Ian,
I use as atribute of one of the instructions the following
define_insn_reservation:
(define_insn_reservation "vmove" 1 "vector_type" "vmove") "c_valu_1|c_vlsu_1")
As you can see vmove has two alternative reservation : c_valu_1 or c_vlsu_1,
where c_valu_1 is defined as follows:
(define
Hello,
Some time ago I asked a question regarding the possibility to schedule an
operation on alternative functional units (FUs) AND depending on the chosen FUs
to generate a dedicated assembly mnemonic.
To give a simple example suppose I have a move operation that can be issued on
one of the
Dear Vladimir,
> Not really. There is no requirement for "the units
> part of the alternatives of a reservation must belong to the
> same automaton". Querying should also work in this
> case because function cpu_unit_reservation_p checks all
> automata for an unit reservation.
Indeed it che
tate.
regards,
Alex
--- On Tue, 3/3/09, Vladimir Makarov wrote:
> From: Vladimir Makarov
> Subject: Re: query automaton
> To: atur...@yahoo.com
> Cc: gcc@gcc.gnu.org
> Date: Tuesday, March 3, 2009, 4:35 PM
> Alex Turjan wrote:
> > Dear Vladimir,
> >
Are there any plans to move the partial unrolling phase from
RTL to Tree-SSA?
The move would benefit from better (or easier to implement) Tree-SSA alias
analysis.
Alex
>
>
>
>
> --- On Wed, 4/22/09, Li Feng
> wrote:
>
> > From: Li Feng
> > Subject: [gSoc] [graphite] general plan for Auto
> For data dependency cases, I do some jobs in
> the adjust_cost target hook.
Normally the scheduling takes into account the instruction latencies which you
have specified: for load 2, for mul 4 and for alu 1.
Why do you need to adjust the sched costs? Did you try simply without adjusting
the c
Hi,
During scheduling Im confronted with the fact that an instruction is moved
from the ready list to queued with the cost 2, while according to my
expectations the insn should have been moved to queued with cost 1.
Did anybody experience similar problem?
In case an insn is ready but can bot be
--- On Thu, 5/7/09, Maxim Kuvyrkov wrote:
> From: Maxim Kuvyrkov
> Subject: Re: scheduling question
> To: atur...@yahoo.com
> Cc: "Vladimir Makarov" , gcc@gcc.gnu.org
> Date: Thursday, May 7, 2009, 1:01 PM
> Alex Turjan wrote:
> > Hi,
> > During schedu
> Do I have to reorganize the code prior to slot filling? Do
> I have to make sure that some problematic instructions do
> not appear in slots?
Perhaps a easy way to solve the problem would be to claim for branches a memory
port a number of stages before and after the IF; to avoid in this way ha
Hi,
My port supports hardware loops generated by the following (do_end) pattern:
(set (pc) (if_then_else (ne (match_operand:HI 0 "general_register_operand" "d")
(const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))
> insns which branch are not allowed to have output
> reloads. You must
> support any kind of register as well as memory operands in
> your insn for
> the loop counter.
Thanks for answer but what do you suggest to do, as my architecture done not
support HW loops with memory operands?
Alex
Hi,
Is there functionality in gcc based on which the CFG can be traversed in such a
way that a node gets visited once all of its predecessors have been visited?
thanks,
Alex
Hi,
I have 3 questions regarding secondary reload:
1.Is it possible to do the secondary reload via 2 intermediary registers?
As far as I can see the insn that implements the secondary reload has to have 3
operands.
2. Is it possible that an instruction emitted during the secondary reload to
ge
Hi Jeff,
Thanks for answer. I managed to make use of an architecture trick which allows
me to get the secondary reload via only one intermediary register, but still
have some comments to what you wrote me.
> > 1.Is it possible to do the secondary reload via 2
> intermediary registers?
> > As far
Hi,
Can anybody give me a hint on where (perhaps some branch) I can find
functionality
which allows during scheduling to un-schedule an instruction? I basically need
a function that does the oposite of schedule_insn.
During scheduling I want o schedule_insn(INSN), then check the ready_list and
Alexander is right. Perhaps you can implement the TARGET_SCHED_ADJUST_COST
, then catch in the debugger the two instructions that you expect to be
scheduled together and see what the default latency is or if needed you
may just adjust it to the proper value.
Alex
--- On Fri, 11/12/10, Alexande
Hi,
I get an assert failure during a run of the selective scheduler.
The problem is due to the implementation of maybe_tidy_empty_bb.
Inside of it I see the following piece of code:
/* If it is possible - merge BB with its predecessor. */
if (can_merge_blocks_p (bb->prev_bb, bb))
sel_merge_blocks
bject: Re: selective scheduler failure
> To: "Alex Turjan"
> Cc: gcc@gcc.gnu.org
> Date: Tuesday, July 17, 2012, 7:07 PM
> > As a consequence inside
> sel_remove_empty_bb I hit on the following assert:
> > gcc_assert (in_current_region_p (merge_bb));
>
> Sou
kov
> Subject: Re: selective scheduler failure
> To: "Alex Turjan"
> Cc: gcc@gcc.gnu.org
> Date: Tuesday, July 17, 2012, 7:57 PM
> On Tue, Jul 17, 2012 at 8:39 PM, Alex
> Turjan
> wrote:
> >
> > Hi,
> > I tried the patch but it doesnt solve my problem.
&g
I applied the new patch and it seams fine.
Thanks!
Alex
--- On Wed, 7/18/12, Alexander Monakov wrote:
> From: Alexander Monakov
> Subject: Re: selective scheduler failure
> To: "Alex Turjan"
> Cc: "Alexander Monakov" , gcc@gcc.gnu.org
> Date: Wednesday, J
Im writing to you with respect to some strange SMS functionality.
In the code bellow there are 2 instructions (a builtin store and a builtin
load)
as they appear in the program flow before SMS:
(insn 134 133 135 12 tdscdma_pfu_ccdec.c:289
(set (mem:HI (plus:PSI (reg/v/f:PSI 185 [ ccdecI
not able to handle such situation... or perhaps there is
something which prevents the modulo scheduler from arriving to this situation?
Alex
--- On Thu, 7/19/12, Andrey Belevantsev wrote:
> From: Andrey Belevantsev
> Subject: Re: SMS issues
> To: "Alex Turjan"
> Cc: g
of an article by Sanjiv Gupta and Naveen
Sharma on alias analysis at the RTL level, which was
published in the GCC 2003 summit. Are there any
further gcc developments of this work or is there a
patch concerning this work?
thanks in advance,
Alex Turjan
Dear Bingfeng,
Some time ago I had to deal with a similar issue as
you. Basically I did as follows: I built a backend
function which catches the unroll pragma and replaces
it with a target assembly intrinsic (which of course
has to be described in an .md file). After that in the
RTL unroll phase, I
gt; do you use for the
> backend function?
>
> -Original Message-
> From: [EMAIL PROTECTED]
> [mailto:[EMAIL PROTECTED] On Behalf Of
> Alex Turjan
> Sent: 29 May 2008 14:45
> To: gcc@gcc.gnu.org
> Subject: RE: Implement #pragma unroll?
>
> Dear Bingfeng,
>
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