Hi all, Im building a gcc target for a vliw machine that can execute the same instruction on different resources (slots) and depending on which resources are allocate the instruction must have a different mnemonic. Is it possible in gcc to have for the same define_insn constraints (depending on the allocated architecture resources) different assembly instructions?
Here is an example: Consider the following addSI RTL pattern: (define_insn "addsi3" [(set (match_operand:SI 0 "general_register_operand" "=d") (plus:SI (match_operand:SI 1 "general_register_operand" "d") (match_operand:SI 2 "general_register_operand" "d")))] "" "add %0,%1,%2%" [(set_attr "type" "alu") (set_attr "mode" "SI") (set_attr "length" "1")]) On my target machine "alu" is a reservation that occupies one of the following 3 slots: "slot1|slot2|slot3" and, I need to generate assembly code with different mnemonic depending on which slot the instruction was scheduled: add-slot1 %0,%1,%2% // if scheduled on slot 1 add-slot2 %0,%1,%2% // if scheduled on slot 2 add-slot3 %0,%1,%2% // if scheduled on slot 3 Alex