Re: Redundant sign-extension instructions on RISC-V

2017-09-06 Thread Richard Henderson
On 08/29/2017 05:36 PM, Michael Clark wrote: > We’re investigating an issue with redundant sign-extension instructions being > emitted with the riscv backend. Firstly I would like to state that riscv is > possibly a unique backend with respect to its canonical sign-extended > register form due t

Re: Redundant sign-extension instructions on RISC-V

2017-09-06 Thread Jeff Law
On 09/06/2017 10:43 AM, Richard Henderson wrote: > On 08/29/2017 05:36 PM, Michael Clark wrote: >> We’re investigating an issue with redundant sign-extension instructions >> being emitted with the riscv backend. Firstly I would like to state that >> riscv is possibly a unique backend with respect

Re: Redundant sign-extension instructions on RISC-V

2017-09-06 Thread Richard Henderson
On 08/30/2017 02:43 AM, Michael Clark wrote: > POINTERS_EXTEND_UNSIGNED -1 (which is true) is defined on some targets. I > assume they sign-extend but the meaning has been overloaded. Just for your edification, this is for e.g. ia64's "addp4" instruction and it is not a normal extension. A 2-bit

Re: Redundant sign-extension instructions on RISC-V

2017-09-06 Thread Richard Henderson
On 09/06/2017 09:53 AM, Jeff Law wrote: >> I think the easiest solution to this is for combine to notice when IOR has >> operands with non-zero-bits that do not overlap, convert the operation to >> ADD. >> That allows the final two insns to fold to "addw" and the compiler need do no >> further ana

Re: Redundant sign-extension instructions on RISC-V

2017-09-06 Thread Richard Henderson
On 09/06/2017 10:17 AM, Richard Henderson wrote: >> Yea. I'd also expect zero/nonzero bits tracking in combine to catch >> this. Shouldn't the sign bit be known to be zero after the shift which >> makes the extension redundant regardless of the SUBREG_PROMOTED flag? > You're right, this should be

Re: Redundant sign-extension instructions on RISC-V

2017-09-06 Thread Jeff Law
On 09/06/2017 11:17 AM, Richard Henderson wrote: > On 09/06/2017 09:53 AM, Jeff Law wrote: >>> I think the easiest solution to this is for combine to notice when IOR has >>> operands with non-zero-bits that do not overlap, convert the operation to >>> ADD. >>> That allows the final two insns to fo

Re: dejagnu version update?

2017-09-06 Thread Jonathan Wakely
On 25 August 2017 at 14:55, David Edelsohn wrote: > On Fri, Aug 25, 2017 at 9:50 AM, Rainer Orth > wrote: >> Hi H.J., >> >>> On Fri, Aug 25, 2017 at 6:32 AM, David Edelsohn wrote: On Fri, Aug 25, 2017 at 9:24 AM, H.J. Lu wrote: > On Fri, Aug 25, 2017 at 6:01 AM, David Edelsohn wrote: >

Re: dejagnu version update?

2017-09-06 Thread David Edelsohn
On Wed, Sep 6, 2017 at 8:48 PM, Jonathan Wakely wrote: > On 25 August 2017 at 14:55, David Edelsohn wrote: >> On Fri, Aug 25, 2017 at 9:50 AM, Rainer Orth >> wrote: >>> Hi H.J., >>> On Fri, Aug 25, 2017 at 6:32 AM, David Edelsohn wrote: > On Fri, Aug 25, 2017 at 9:24 AM, H.J. Lu wrote:

gcc-6-20170906 is now available

2017-09-06 Thread gccadmin
Snapshot gcc-6-20170906 is now available on ftp://gcc.gnu.org/pub/gcc/snapshots/6-20170906/ and on various mirrors, see http://gcc.gnu.org/mirrors.html for details. This snapshot has been generated from the GCC 6 SVN branch with the following options: svn://gcc.gnu.org/svn/gcc/branches/gcc-6

Re: [llvm-dev] DragonEgg for GCC v8.x and LLVM v6.x is just able to work

2017-09-06 Thread Chris Lattner
> On Sep 4, 2017, at 8:13 PM, Leslie Zhai via llvm-dev > wrote: > > Hi LLVM and GCC developers, > > LLVM China http://www.llvm.org.cn forked DragonEgg > https://github.com/LLVM-China/dragonegg because: > > * Some subprojects are impractical or uninteresting to relicense (e.g. > llvm-gcc

Power 8 in-core crypto not working as expected

2017-09-06 Thread Jeffrey Walton
Hi Everyone, I'm on gcc rather than gcc-help because we need to talk with some GCC devs who can help take this further. I have implementation for AES on Power 8 using GCC's built-ins. Its available for inspection and download at https://github.com/noloader/AES-Power8. The problem is, it does not

Re: [llvm-dev] DragonEgg for GCC v8.x and LLVM v6.x is just able to work

2017-09-06 Thread Leslie Zhai
Dear Chris, Thanks for your kind response! The motivating of this work: 1. Clang can not build Linux https://bugs.llvm.org/show_bug.cgi?id=22830 and LLVMLinux patch was not be maintained? http://llvm.linuxfoundation.org/index.php/Main_Page 2. Clang analyzer Frontend can not static analysis

Re: Power 8 in-core crypto not working as expected

2017-09-06 Thread R0b0t1
On Wed, Sep 6, 2017 at 11:37 PM, Jeffrey Walton wrote: > Hi Everyone, > > I'm on gcc rather than gcc-help because we need to talk with some GCC > devs who can help take this further. > > I have implementation for AES on Power 8 using GCC's built-ins. Its > available for inspection and download at

Re: Power 8 in-core crypto not working as expected

2017-09-06 Thread Jeffrey Walton
On Thu, Sep 7, 2017 at 1:39 AM, R0b0t1 wrote: > On Wed, Sep 6, 2017 at 11:37 PM, Jeffrey Walton wrote: >> Hi Everyone, >> >> I'm on gcc rather than gcc-help because we need to talk with some GCC >> devs who can help take this further. >> >> I have implementation for AES on Power 8 using GCC's bui