Hi,
I am trying to fuse two loops in tree level. For that, I am trying to
transfer statements in the header of one loop to the header of the
other one.
The code " http://rafb.net/p/fha0IG57.html " contains the 2 loops.
After moving a statement from one BB to another BB, do I need to
update any
Hi,
While running testsuite for target x86_64-pc-mingw32, I noticed that the
stack segement has for this target no execution permission. May somebody
could help me, how to avoid the use of stack based trampoline code.
Do you know how to avoid this HJ?
Thanks in advance,
Kai
| (\_/) This is
I got a request to change gcc/assembler option, which enables
PCLMULQDQ, from -mclmul to -mpclmul, to reflect packed operation.
Is there any objection?
Thanks.
H.J.
Hi,
> I am trying to fuse two loops in tree level. For that, I am trying to
> transfer statements in the header of one loop to the header of the
> other one.
> The code " http://rafb.net/p/fha0IG57.html " contains the 2 loops.
> After moving a statement from one BB to another BB, do I need to
Kai Tietz <[EMAIL PROTECTED]> writes:
> While running testsuite for target x86_64-pc-mingw32, I noticed that the
> stack segement has for this target no execution permission. May somebody
> could help me, how to avoid the use of stack based trampoline code.
> Do you know how to avoid this HJ?
F
On Fri, Apr 4, 2008 at 6:18 AM, H.J. Lu <[EMAIL PROTECTED]> wrote:
> I got a request to change gcc/assembler option, which enables
> PCLMULQDQ, from -mclmul to -mpclmul, to reflect packed operation.
> Is there any objection?
>
> Thanks.
>
Hi,
I am checking in this patch to change clmul/CLMUL t
Hi,
For each new set of x86 intrinsics, we introduce a new header file. It
will be desirable for users just to include one header file for all
intrinsics, current and future. Icc has , which includes
proper individual intrinsic header files and users just need
to include to get access to all intr
Tom Tromey and I were chatting on IRC about the possibility of having
a Just-For-Fun awards ceremony at the GCC Summit where we would honor
folks in the community that have done some kind of positive
contribution to GCC (obviously a slow day for both of us).
The recipients would receive some sort
On Fri, Apr 4, 2008 at 10:13 AM, Diego Novillo <[EMAIL PROTECTED]> wrote:
> Tom Tromey and I were chatting on IRC about the possibility of having
> a Just-For-Fun awards ceremony at the GCC Summit where we would honor
> folks in the community that have done some kind of positive
> contribution t
On Fri, Apr 4, 2008 at 10:13 AM, Diego Novillo <[EMAIL PROTECTED]> wrote:
> > Tom Tromey and I were chatting on IRC about the possibility of having
> > a Just-For-Fun awards ceremony at the GCC Summit where we would honor
> > folks in the community that have done some kind of positive
> > contr
On Apr 4, 2008, at 10:13 AM, H.J. Lu wrote:
Hi,
For each new set of x86 intrinsics, we introduce a new header file. It
will be desirable for users just to include one header file for all
intrinsics, current and future. Icc has , which includes
proper individual intrinsic header files and users
On Fri, Apr 4, 2008 at 10:58 AM, Chris Lattner <[EMAIL PROTECTED]> wrote:
>
>
> On Apr 4, 2008, at 10:13 AM, H.J. Lu wrote:
>
>
> > Hi,
> >
> > For each new set of x86 intrinsics, we introduce a new header file. It
> > will be desirable for users just to include one header file for all
> > intrins
I prefer , as these are presumably usable in x86-64
mode.
One random request: would it be possible to keep mm_malloc.h out of
the
umbrella header? Inclusion of mm_malloc.h make use of SSE
difficult in
kernel contexts, as mm_malloc.h pulls in stdlib.h and errno.h.
The idea is one header
I posted Ada ACATS results this morning for 4 targets
(i386, powerpc, sparc, and mips) to gcc-testresults.
In general, they were very good -- the powerpc only
had 3 ACATS failures and those were cross target.
Compiler version:
4.4.0 20080403 (experimental) [trunk revision 133868]
The sparc ha
On Fri, Apr 04, 2008 at 11:35:00AM -0700, Chris Lattner wrote:
>>> I prefer , as these are presumably usable in x86-64 mode.
>>>
>>> One random request: would it be possible to keep mm_malloc.h out of the
>>> umbrella header? Inclusion of mm_malloc.h make use of SSE difficult in
>>> kernel context
> Have you tried running valgrind?
Thanks for the tip. Indeed something shows up:
Compiler executable checksum: 87aef5f5c9fba1ed8f2a556528fc3927
==3282== Conditional jump or move depends on uninitialised value(s)
==3282==at 0x904EFA6: aligned_operand_1 (predicates.md:820)
==3282==by 0x90
On Fri, 4 Apr 2008, Joe Buck wrote:
> No, you get the award for memorizing the Bugzilla database.
Yeah, let's do a quiz with questions of the kind "Which releases and
architectures does Bugzilla X affect". :-)
Seriously, go for it, Tom and Diego!
Gerald
Apologies if this has been discussed before. I built the ARM compiler
for gcc-3.4.1 and gcc-4.2.2, and there seems to be a performance
regression. A tight loop in gcc-3.4.1 generates better code than
gcc-4.2.2.
In gcc-4.2.2, the store to the memory location of variable 'p' happens
in the loop. Ho
Snapshot gcc-4.4-20080404 is now available on
ftp://gcc.gnu.org/pub/gcc/snapshots/4.4-20080404/
and on various mirrors, see http://gcc.gnu.org/mirrors.html for details.
This snapshot has been generated from the GCC 4.4 SVN branch
with the following options: svn://gcc.gnu.org/svn/gcc/trunk
Xilinx has a PowerPC 405 processor with an attached
single precision floating point processor. I have a
patch which supports this FP unit, but want to clean
it up a bit before submitting it.
There are a number of different flags which are used
to specify different FP support. I'd like to simpli
no_trampolines Dejagnu switch will omit many but not all trampoline dependent
tests.
Nested function are ok - but anything that takes an address of a nested function will use trampoline.
They can be hard to find as testcases are devilish at hiding that part!
For example:
gcc.c-torture/com
I have Sempron processor with SSE3 support, but the march=native seems
to ommit the -msse3 option:
--
> cat /proc/cpuinfo
--
processor : 0
vendor_id
I noticed that we are failing...
FAIL: 27_io/ios_base/storage/11584.cc execution test
in the libstdc++ testsuite on i686-apple-darwin9 in
gcc 4.3 branch and gcc 4.3.0. However we stopped failing
this in gcc trunk by r132965...
http://gcc.gnu.org/ml/gcc-testresults/2008-03/msg00427.html
and t
I narrowed it down to commit 133403 (although whether that caused the
bug or merely expose it, I don't know):
2008-03-21 Richard Guenther <[EMAIL PROTECTED]>
* tree-scalar-evolution.c (chrec_contains_symbols_defined_in_loop):
Use is_gimple_min_invariant instead of TREE_INVARIA
I would prefer feature-based.
TARGET_HARD_FLOAT represents the presence of FPUs.
TARGET_FPRS represents the presence of FP register set because
one variant used GPRs for FP operations.
E500 then added another variant with double-precision FP in the
GPRs.
>
> if (parts.base)
> {
> if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32) <-- 820
> return 0;
> }
>
> I think parts.base is OK so it's probably REGNO_POINTER_ALIGN
Uh, while converting the regno_pointer_align from GGC to malloced
memory, I mistakely used xmalloc instead
Hello!
> I have Sempron processor with SSE3 support, but the march=native seems to
> ommit the -msse3 option:
This was fixed in 4.3.0.
Uros.
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