On 23-May-14 05:20 PM, Vladimir Makarov wrote:
On 2014-05-23, 3:49 AM, shmeel gutl wrote:
On 21-May-14 06:30 PM, Vladimir Makarov wrote:
I am just curious what happens when you put
insn2, insn1.
and insn2 uses a result of insn1 in 6 cycles and insn1 producing the
result in 3 cycles, but there
On 23-May-14 01:59 PM, Bernd Schmidt wrote:
On 05/23/2014 10:07 AM, shmeel gutl wrote:
Exposed pipeline is not my problem. Negative latency is my problem. I
don't see negative latency for c6x, not in unit reservations and not in
adjust cost. Did I miss something?
You just need to model it dif
On 2014-05-23, 3:49 AM, shmeel gutl wrote:
On 21-May-14 06:30 PM, Vladimir Makarov wrote:
I am just curious what happens when you put
insn2, insn1.
and insn2 uses a result of insn1 in 6 cycles and insn1 producing the
result in 3 cycles, but there are not ready functional units (e.g.
arithmenti
On 05/23/2014 10:07 AM, shmeel gutl wrote:
Exposed pipeline is not my problem. Negative latency is my problem. I
don't see negative latency for c6x, not in unit reservations and not in
adjust cost. Did I miss something?
You just need to model it differently. Rather than saying instruction A
h
On 22-May-14 07:21 PM, Bernd Schmidt wrote:
On 05/21/2014 05:30 PM, Vladimir Makarov wrote:
On 2014-05-20, 5:18 PM, shmeel gutl wrote:
The problem that I see is that the haifa scheduler schedules one cycle
at a time, in a forward order, by picking from a list of instructions
that can be schedul
On 21-May-14 06:30 PM, Vladimir Makarov wrote:
I am just curious what happens when you put
insn2, insn1.
and insn2 uses a result of insn1 in 6 cycles and insn1 producing the
result in 3 cycles, but there are not ready functional units (e.g.
arithmentic units) necessary for insn1 for 4 or more
On 05/21/2014 05:30 PM, Vladimir Makarov wrote:
On 2014-05-20, 5:18 PM, shmeel gutl wrote:
The problem that I see is that the haifa scheduler schedules one cycle
at a time, in a forward order, by picking from a list of instructions
that can be scheduled without delays. So, in the above example,
On 2014-05-20, 5:18 PM, shmeel gutl wrote:
On 20-May-14 06:13 PM, Vladimir Makarov wrote:
On 05/19/2014 02:13 AM, shmeel gutl wrote:
Are there hooks in gcc to deal with negative latencies? In other
words, an architecture that permits an instruction to use a result
from an instruction that will
On 20-May-14 06:13 PM, Vladimir Makarov wrote:
On 05/19/2014 02:13 AM, shmeel gutl wrote:
Are there hooks in gcc to deal with negative latencies? In other
words, an architecture that permits an instruction to use a result
from an instruction that will be issued later.
Could you explain more
On 05/19/2014 02:13 AM, shmeel gutl wrote:
> Are there hooks in gcc to deal with negative latencies? In other
> words, an architecture that permits an instruction to use a result
> from an instruction that will be issued later.
>
Could you explain more on *an example* what are y
On 19-May-14 01:02 PM, Ajit Kumar Agarwal wrote:
Is it the case of code speculation where the negative latencies are used?
No. It is an exposed pipeline where instructions read registers during
the required cycle. So if one instruction produces its results in the
third pipeline stage and a
Is it the case of code speculation where the negative latencies are used?
Thanks & Regards
Ajit
-Original Message-
From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of shmeel
gutl
Sent: Monday, May 19, 2014 12:23 PM
To: Andrew Pinski
Cc: gcc@gcc.gnu.org; Vlad
On 19-May-14 09:39 AM, Andrew Pinski wrote:
On Sun, May 18, 2014 at 11:13 PM, shmeel gutl
wrote:
Are there hooks in gcc to deal with negative latencies? In other words, an
architecture that permits an instruction to use a result from an instruction
that will be issued later.
Do you mean
On Sun, May 18, 2014 at 11:13 PM, shmeel gutl
wrote:
> Are there hooks in gcc to deal with negative latencies? In other words, an
> architecture that permits an instruction to use a result from an instruction
> that will be issued later.
Do you mean bypasses? If so there is a bypas
Are there hooks in gcc to deal with negative latencies? In other words,
an architecture that permits an instruction to use a result from an
instruction that will be issued later.
At first glance it seems that it will will break a few things.
1) The definition of dependencies cannot come from
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