2010/8/1 redriver jiang :
> Hi Denis,
>
> I read the "out_movqi_r_mr" code of the AVR port. I see that following
> exception are
>
> handled:
>
> 1. "REG_X+offset", which is not supported by AVR.
> 2. "REGY+offset", with offset larger than 63, which is not supported by AVR.
>
> Seems reload can not
Hi Denis,
I read the "out_movqi_r_mr" code of the AVR port. I see that following
exception are
handled:
1. "REG_X+offset", which is not supported by AVR.
2. "REGY+offset", with offset larger than 63, which is not supported by AVR.
Seems reload can not handle the targets that has some base regs
2010/7/31 redriver jiang :
> Hi,
>
> Seems there are still some exceptions.
>
> During my testing, the compiler complains:
>
> ./os_core.c: In function 'OS_EventTaskWait':
> ./os_core.c:747: error: unable to find a register to spill in class
> 'POINTER_REGS'
> ./os_core.c:747: error: this is the in
Hi,
Seems there are still some exceptions.
During my testing, the compiler complains:
./os_core.c: In function 'OS_EventTaskWait':
./os_core.c:747: error: unable to find a register to spill in class
'POINTER_REGS'
./os_core.c:747: error: this is the insn:
(insn 7 6 8 2 ./os_core.c:739 (set (mem/
redriver jiang writes:
> But the constrains are really long.
Well, yeah.
> I use "U" for memory operands with address "R18+offset", and "S" for
> memory operands with address "R16" or "R17", and "Q" for memory
> operands with constant address(such as symbol ref, or const_int), the
> all combina
Hi, it works.
But the constrains are really long.
I use "U" for memory operands with address "R18+offset", and "S" for
memory operands with address "R16" or "R17", and "Q" for memory
operands with constant address(such as symbol ref, or const_int), the
all combinations are as more as 43 types, an
redriver jiang writes:
> Hi,
>
> You mean I should define insn like this:
>
> (define_insn "*iorqi3_imm"
> [(set (mem:QI (match_operand:HI 0 "register_operand" "b"))
>(ior:QI (mem:QI (match_operand:HI 1 "register_operand" "b")
> (mem:QI (plus: HI (match_opera
Hi,
You mean I should define insn like this:
(define_insn "*iorqi3_imm"
[(set (mem:QI (match_operand:HI 0 "register_operand" "b"))
(ior:QI (mem:QI (match_operand:HI 1 "register_operand" "b")
(mem:QI (plus: HI (match_operand:HI 2
"register_operand" "f")
Hi,
You mean I should define insn like this:
(define_insn "*iorqi3_imm"
[(set (mem:QI (match_operand:HI 0 "register_operand" "b"))
(ior:QI (mem:QI (match_operand:HI 1 "register_operand" "b")
(mem:QI (plus: HI (match_operand:HI 2 "register_operand"
"f")
redriver jiang writes:
> I am porting GCC to a 8bit architecture, and now I have problem on
> reload problem on addressing mode.
> Besides 15 general registers, it has three 16bit address registers,
> R16,R17,R18.
> R16,R17,R18 are able to be as base register in "base" address mode,
> but only R1
Hi,
I am porting GCC to a 8bit architecture, and now I have problem on
reload problem on addressing mode.
Besides 15 general registers, it has three 16bit address registers,
R16,R17,R18.
R16,R17,R18 are able to be as base register in "base" address mode,
but only R18 can be base regs for "base+off
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