Balaji S <[EMAIL PROTECTED]> writes:
> >>So you have a few instructions bundled into a VLIW instruction, and
> >>one of the instructions in the bundle is moved into the delay slot,
> >>thus breaking your VLIW bundle. Right?
> > I think there are two natural approaches.
> > 1) Do the VLIW bundling
Ian Lance Taylor writes:
> Steven Bosscher <[EMAIL PROTECTED]> writes:
>> So you have a few instructions bundled into a VLIW instruction, and
>> one of the instructions in the bundle is moved into the delay slot,
>> thus breaking your VLIW bundle. Right?
>
> I think there are two natural approach
_On 05-Jul-2005 00:14, Ian Lance Taylor san wrote_:
Steven Bosscher <[EMAIL PROTECTED]> writes:
So you have a few instructions bundled into a VLIW instruction, and
one of the instructions in the bundle is moved into the delay slot,
thus breaking your VLIW bundle. Right?
I think there are tw
Steven Bosscher <[EMAIL PROTECTED]> writes:
> So you have a few instructions bundled into a VLIW instruction, and
> one of the instructions in the bundle is moved into the delay slot,
> thus breaking your VLIW bundle. Right?
I think there are two natural approaches.
1) Do the VLIW bundling afte
So you have a few instructions bundled into a VLIW instruction, and
one of the instructions in the bundle is moved into the delay slot,
thus breaking your VLIW bundle. Right?
That is a much harder problem... I don't think it is really possible
with the existing dbr scheduling pass, but maybe
On Monday 04 July 2005 12:41, Balaji S wrote:
> _On 04-Jul-2005 15:31, Steven Bosscher san wrote_:
> > Add an attribute to those instructions that cannot be in delay slots,
> > and change this define_delay to disallow instructions with that attr?
>
> Any instruction other than jump can be placed in
_On 04-Jul-2005 15:31, Steven Bosscher san wrote_:
Add an attribute to those instructions that cannot be in delay slots,
and change this define_delay to disallow instructions with that attr?
Any instruction other than jump can be placed in the delay slot. I hope "!jump"
can fulfill this requi
On Monday 04 July 2005 07:59, Balaji S wrote:
> Hi everybody,
>
> I have a problem with delayed branch scheduling. Problem in a DSP porting
> which has VLIW instructions and delayed branches. While scheduling delayed
> branches, GCC (3.4.3) schedules an instruction which is a
Hi everybody,
I have a problem with delayed branch scheduling. Problem in a DSP porting which
has VLIW instructions and delayed branches. While scheduling delayed branches,
GCC (3.4.3) schedules an instruction which is a part of a VLIW instruction. Is
this the problem of the following
