Balaji S <[EMAIL PROTECTED]> writes: > >>So you have a few instructions bundled into a VLIW instruction, and > >>one of the instructions in the bundle is moved into the delay slot, > >>thus breaking your VLIW bundle. Right? > > I think there are two natural approaches. > > 1) Do the VLIW bundling after delayed branch scheduling. The way to > > do that is to the bundling in TARGET_ASM_FUNCTION_PROLOGUE. The > > FRV backend does this. I've done this successfully in the past. > I think this is a good workaround but nullifying the possibility of having a > VLIW bundled instruction in a branch delay slot.
Well, you can have multiple instructions in a delay slot by pretending that there are multiple delay slots. You have to write the delay slot conditions such that the selected instructions can always form a bundle. This is clearly getting a little tricky. > > 2) When you do the VLIW bundling, put the instructions into a > > PARALLEL. > I think this is the right solution which rectifies the problems. Please > provide the pointer to where it has to be done. I've never actually done it this way myself. I guess the TARGET_SCHED_FINISH hook would be the place to tie the instructions together. Ian
