nd bb structure.
Hope this helps,
Tomer
-Original Message-
From: Richard Guenther [mailto:[EMAIL PROTECTED]
Sent: Tuesday, March 18, 2008 19:47
To: Boris Boesler
Cc: Jim Wilson; GCC
Subject: Re: Basic block infrastructure after dbr pass
On Tue, Mar 18, 2008 at 6:40 PM, Boris Boesler &l
Boris Boesler wrote:
I haven't specified my problem properly? If I traverse basic blocks via
FOR_EACH_BB (used in compute_bb_for_insn, too) I get insns which are not
in the insn-stream for(insn = get_insns(), insn; insn = NEXT_INSN(insn)) ..
As Ian mentioned, the delay-slot filling pass does
Am 18.03.2008 um 18:47 schrieb Richard Guenther:
On Tue, Mar 18, 2008 at 6:40 PM, Boris Boesler <[EMAIL PROTECTED]> wrote:
Am 18.03.2008 um 16:21 schrieb Jim Wilson:
Boris Boesler wrote:
The following code generators use FOR_EACH_BB[_REVERSE] in the
target machine dependent reorg pass:
On Tue, Mar 18, 2008 at 6:40 PM, Boris Boesler <[EMAIL PROTECTED]> wrote:
> Am 18.03.2008 um 16:21 schrieb Jim Wilson:
>
> > Boris Boesler wrote:
> >> The following code generators use FOR_EACH_BB[_REVERSE] in the
> >> target machine dependent reorg pass:
> >> - bfin
> >> - frv
> >>
Am 18.03.2008 um 16:21 schrieb Jim Wilson:
Boris Boesler wrote:
The following code generators use FOR_EACH_BB[_REVERSE] in the
target machine dependent reorg pass:
- bfin
- frv
- ia64
- mt
- s390
The very first thing that ia64_reorg does is
compute_bb_for_insn ();
F
Bernd Schmidt <[EMAIL PROTECTED]> writes:
> Ian Lance Taylor wrote:
>> Boris Boesler <[EMAIL PROTECTED]> writes:
>>
>>> The following code generators use FOR_EACH_BB[_REVERSE] in the
>>> target machine dependent reorg pass:
>>> - bfin
>>> - frv
>>> - ia64
>>> - mt
>>> - s390
>
Ian Lance Taylor wrote:
Boris Boesler <[EMAIL PROTECTED]> writes:
The following code generators use FOR_EACH_BB[_REVERSE] in the
target machine dependent reorg pass:
- bfin
- frv
- ia64
- mt
- s390
Are these invalid code generators then? Or are we talki
Boris Boesler wrote:
The following code generators use FOR_EACH_BB[_REVERSE] in the target
machine dependent reorg pass:
- bfin
- frv
- ia64
- mt
- s390
The very first thing that ia64_reorg does is
compute_bb_for_insn ();
Just taking a quick look, I don't see any bb us
Boris Boesler <[EMAIL PROTECTED]> writes:
> The following code generators use FOR_EACH_BB[_REVERSE] in the
> target machine dependent reorg pass:
> - bfin
> - frv
> - ia64
> - mt
> - s390
> Are these invalid code generators then? Or are we talking about
> different
Am 17.03.2008 um 17:45 schrieb Jim Wilson:
Boris Boesler wrote:
But some basic blocks seem to point to insns which are not in the
insn-list. I had a short look at dbr_schedule() in reorg.c and the
basic blocks are not updated. Are they evaluated in a later pass?
No. See pass_free_cfg, wh
Boris Boesler wrote:
But some basic blocks seem to point to insns which are not in the
insn-list. I had a short look at dbr_schedule() in reorg.c and the basic
blocks are not updated. Are they evaluated in a later pass?
No. See pass_free_cfg, which is the third pass before pass_delay_slots.
Hi!
I inspect code after branch delay slot scheduling by dumping the
insn-list to a VCG-file:
for(insn = get_insns(), NULL_RTX != insn; insn = NEXT_INSN(insn))
dump_insn_and_prev_and_next(insn);
FOR_EACH(bb) dump_bb_and_head_and_end(bb)
But some basic blocks seem to point to insns which a
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