As an example, combine pass is based on outdated work of Fraser,
Proebsting etc.
And combine is useful for ia64 because...? Alternatives for combine
exist for targets with relatively simple ISAs with few parallels.
While it is true that combine is not a very good algorithm, combine is
not
On Tuesday 15 November 2005 19:59, Mark K. Smith wrote:
> RTL is too complicated. On Andrew Macleod and my etsimation only
> writing a new good register allocator is at least 2 years project.
> Significtant simplifying rtl or usage another IR is even more
> complicated task than introducing Tree-SS
On 11/15/05, Andrew Pinski <[EMAIL PROTECTED]> wrote:
> > I told about importance of early access to machines based on new
> > Itanium chip (Montecito) and documentation for gcc developers trying
> > to improve gcc for Itanium.
> >
> > As for Mark Davis remark about rewriting RTL optimizations, I t
>
> > I told about importance of early access to machines based on new
> > Itanium chip (Montecito) and documentation for gcc developers trying
> > to improve gcc for Itanium.
> >
> > As for Mark Davis remark about rewriting RTL optimizations, I told
> > that it can not be done easily.
>
> HUH?
> I told about importance of early access to machines based on new
> Itanium chip (Montecito) and documentation for gcc developers trying
> to improve gcc for Itanium.
>
> As for Mark Davis remark about rewriting RTL optimizations, I told
> that it can not be done easily.
HUH? An example of some
ON THE CALL: Shin-ming Liu (HP), Vladimir Makarov (Red Hat), Diego
Novillo (Red Hat), Mark Smith (Gelato), Andrey Belevantsev (RAS),
Arutyun Avetisyan (RAS), Bob Kidd (UIUC), Mark Davis (Intel)
The call covered:
1. Setting up GCC branch for Itanium-related work
2. Alias analysis update from RAS an
