On Tuesday 15 November 2005 19:59, Mark K. Smith wrote: > RTL is too complicated. On Andrew Macleod and my etsimation only > writing a new good register allocator is at least 2 years project. > Significtant simplifying rtl or usage another IR is even more > complicated task than introducing Tree-SSA because machine description > is very tied to RTL.
Is RTL complicated, or is working with RTL complicated? It seems to me that the kind of optimizations we ought to be doing should be doable on RTL (but perhaps register allocation is obviously a harder problem on RTL than on other IRs?). > As an example, combine pass is based on outdated work of Fraser, > Proebsting etc. And combine is useful for ia64 because...? Alternatives for combine exist for targets with relatively simple ISAs with few parallels. E.g. Paolo Bonzini's fwprop pass. > (e.g. reload assumes that all > moves/stores/loads of one mode is described by one define_insn > pattern). I secretly still hope that an RA without reload-as-we-know-it is possible. The new-ra branch, regardless of what people may think of that allocator, the number of reloads was almost zero due to the pre-reload pass. Which was ugly, but as a proof-of-concept I think it was quite successful. Gr. Steven
