C-family stack check for threads

0, =stack_limit_var ->ldrr0, [r0] ->cmpsp, r0 ->bhs1f ->push{lr} ->bl__thumb_stack_failure@ stack check ->.align ->.ltorg ->1: ->pop{r0} The rest of the implementation overhead is only GCC specific. Regards

Request for clarification on how a contribution to gcc can be made

Hello To me it looks like that what is described in the online document is either not correct or is being misinterpreted at least by me. It's not clear to me at which point the FSF is trusting an individual (or organization or company) and why it is mistru

Add static size report when using -fstack-usage for ARM targets

Hello With GCC 4.6 a new switch -fstack-usage has been added. Some target architectures have support for this. To give ARM targets support for this feature only a few lines of code are missing. Is it possible to add this or something similar? regards Thomas 2010-11-21 Thomas Klein

RE: TLS support on ARM

Hello > > But is this true? > It is true because a typical implementation of this function has no > need to clobber registers. For instance, glibc's calls a kernel > helper this way: Ah. now I understand, you require to have a virtual memory system (or similar) that is translating the call in

RE: TLS support on ARM

Hello > > Dose anyone know the reason why they are not clobbered? > > So that they don't have to be saved. This function is supposed to be > very fast. If you want to use a slow implementation, write an > assembly wrapper which saves additional registers. This might be the initial plan. But is

TLS support on ARM

Hello To me it looks like, that support for Thread Local Storage exists on ARM cpu's. When needed the compiler is going to fetch the base pointer by a internal __builtin_thread_pointer() call. This is either a call to __aeabi_read_tp() or a Coprocessor fetch instruction. If I'm going to impl