Hello
To me it looks like, that support for Thread Local Storage exists on ARM
cpu's.
When needed the compiler is going to fetch the base pointer by a
internal __builtin_thread_pointer() call.
This is either a call to __aeabi_read_tp() or a Coprocessor fetch
instruction.
If I'm going to implement __aeabi_read_tp() as a standard C-function, I
will get in trouble since the registers r1 to r3 are not saved before.
This behaviour is commented in file arm.md:
"..
;; Doesn't clobber R1-R3. Must use r0 for the first operand.
(define_insn "load_tp_soft"
..
"
Dose anyone know the reason why they are not clobbered?
Is there a way to save r1-r3 at function entry? (e.g.
__attribute__((save_noreturn_args)) )
The next point is that the __builtin_thread_pointer() call isn't
ARM/Thumb interwork save.
To use the "hard" Coprocessor fetch instruction the calling function
must run in ARM mode.
To use "soft" implementation caller and __aeabi_read_tp() must run in
the same mode.
Is the implementation still incomplete?
regards
Thomas
