Re: GSoC 2025: In-Memory Filesystem for GPU Offloading Tests

On 10/03/2025 15:37, Arijit Kumar Das via Gcc wrote: Hello GCC Community! I am Arijit Kumar Das, a second-year engineering undergraduate from NIAMT Ranchi, India. While my major isn’t Computer Science, my passion for system programming, embedded systems, and operating systems has driven me towar

Re: GSoC 2025: In-Memory Filesystem for GPU Offloading Tests

On 10/03/2025 22:56, Arijit Kumar Das wrote: Hello Andrew, Thank you for the detailed response! This gives me a much clearer picture of how things work. Regarding the two possible approaches: * I personally find *Option A (self-contained in-memory FS)* more interesting, and I'd like to

Re: Help for git send-email setting

On 13/01/2025 01:27, Hao Liu via Gcc wrote: Hi, I'm new to GCC community, and try to contribute some patches. I am having trouble setting git send-email with Outlook on Linux. Does anyone have any successful experiences to share? I assume from your email address that you're referring to the

Re: [RFC] Enabling SVE with offloading to nvptx

On 27/12/2024 12:29, Prathamesh Kulkarni wrote: -Original Message- From: Jakub Jelinek Sent: 17 December 2024 19:09 To: Prathamesh Kulkarni Cc: Andrew Stubbs ; Richard Biener ; Richard Biener ; gcc@gcc.gnu.org; Thomas Schwinge Subject: Re: [RFC] Enabling SVE with offloading to

Re: [RFC] Enabling SVE with offloading to nvptx

On 12/11/2024 06:01, Prathamesh Kulkarni via Gcc wrote: -Original Message- From: Jakub Jelinek Sent: 04 November 2024 21:44 To: Prathamesh Kulkarni Cc: Richard Biener ; Richard Biener ; gcc@gcc.gnu.org; Thomas Schwinge Subject: Re: [RFC] Enabling SVE with offloading to nvptx Extern

Re: [RFC] Enabling SVE with offloading to nvptx

amdgcn has V16 modes the baseline result is much better, but max_vf really does need to be 64.From 69db90d5639c4ce082136eee032ab63a61a32035 Mon Sep 17 00:00:00 2001 From: Andrew Stubbs Date: Mon, 21 Oct 2024 12:29:54 + Subject: [PATCH 1/3] openmp: Tune omp_max_vf for offload targets If requ

Re: [RFC] MAINTAINERS: require a BZ account field

On 25/06/2024 10:05, Arsen Arsenović wrote: Hi, Andrew Stubbs writes: On 24/06/2024 23:34, Arsen Arsenović via Gcc wrote: I was also proposing (and would like to re-air that here) enforcing that the committer field of each commit is a (valid) @gcc.gnu.org email. This can be configured repo

Re: [RFC] MAINTAINERS: require a BZ account field

On 24/06/2024 23:34, Arsen Arsenović via Gcc wrote: I was also proposing (and would like to re-air that here) enforcing that the committer field of each commit is a (valid) @gcc.gnu.org email. This can be configured repo-locally via: $ git config committer.email @gcc.gnu.org Git has supporte

Register allocation problem

Hi all, I'm trying to solve an infinite loop in the "reload" pass (LRA). I need early-clobber on my load instructions and it goes wrong when register pressure is high. Is there a proper way to fix this? Or do I need to do something "hacky" like fixing a register for use with reloads? Here'

Re: Register allocation cost question

On 10/10/2023 20:09, Segher Boessenkool wrote: Hi Andrew, On Tue, Oct 10, 2023 at 04:11:18PM +0100, Andrew Stubbs wrote: I'm also seeing wrong-code bugs when I allow more than 32 new registers, but that might be an unrelated problem. Or the allocation is broken? I'm still analyzing

Re: Register allocation cost question

On 11/10/2023 07:54, Chung-Lin Tang wrote: On 2023/10/10 11:11 PM, Andrew Stubbs wrote: Hi all, I'm trying to add a new register set to the GCN port, but I've hit a problem I don't understand. There are 256 new registers (each 2048 bit vector register) but the register

Re: Register allocation cost question

On 10/10/2023 20:09, Segher Boessenkool wrote: Hi Andrew, On Tue, Oct 10, 2023 at 04:11:18PM +0100, Andrew Stubbs wrote: I'm also seeing wrong-code bugs when I allow more than 32 new registers, but that might be an unrelated problem. Or the allocation is broken? I'm still anal

Register allocation cost question

Hi all, I'm trying to add a new register set to the GCN port, but I've hit a problem I don't understand. There are 256 new registers (each 2048 bit vector register) but the register file has to be divided between all the running hardware threads; if you can use fewer registers you can get mo

Re: Test with an lto-build of libgfortran.

On 28/09/2023 20:59, Toon Moene wrote: On 9/28/23 21:26, Jakub Jelinek wrote: It is worse than that, usually the LTO format changes e.g. any time any option or parameter is added on a release branch (several times a year) and at other times as well. Though, admittedly GCC is the single packag

Re: Clarification on newlib version for building AMDGCN offloading backend

On 29/03/2023 19:18, Wileam Yonatan Phan wrote: Hi Andrew, I just built GCC 12.2.0 with AMDGCN offloading successfully with Spack! However, when I tried to test it with an OpenACC test code that I have, I encountered the following error message: wyp@basecamp:~/work/testcodes/f90-acc-ddot$ gfor

Re: Libgcc divide vectorization question

On 22/03/2023 13:56, Richard Biener wrote: Basically, the -ffast-math instructions will always be the fastest way, but the goal is that the default optimization shouldn't just disable vectorization entirely for any loop that has a divide in it. We try to express division as multiplication, but

Re: Libgcc divide vectorization question

On 22/03/2023 10:09, Richard Biener wrote: On Tue, Mar 21, 2023 at 6:00 PM Andrew Stubbs wrote: Hi all, I want to be able to vectorize divide operators (softfp and integer), but amdgcn only has hardware instructions suitable for -ffast-math. We have recently implemented vector versions of

Libgcc divide vectorization question

Hi all, I want to be able to vectorize divide operators (softfp and integer), but amdgcn only has hardware instructions suitable for -ffast-math. We have recently implemented vector versions of all the libm functions, but the libgcc functions aren't builtins and therefore don't use those hoo

Re: Clarification on newlib version for building AMDGCN offloading backend

On 06/03/2023 19:23, Wileam Yonatan Phan via Gcc wrote: Hi, I'm working on adding a build recipe for GCC with AMDGCN offloading backend in Spack. Can anyone clarify the following sentence listed on the wiki? The Newlib version needs to be contemporaeous with GCC, at least until the ABI is fi

Re: Complex multiply optimization working?

On 11/04/2022 13:03, Tamar Christina wrote: They work fine in both GCC 11 and HEAD https://godbolt.org/z/Mxxz6qWbP Did you actually enable the instructions? Yes, as I said it uses the instructions, just not fully vectorized. Anyway, the problem was I needed -ffast-math to skip the NaN checks.

Re: Complex multiply optimization working?

On 11/04/2022 13:02, Richard Biener wrote: You need to check the vectorizer dump whether a complex pattern was recognized or not. Did you properly use -ffast-math? Aha! I needed to enable -ffast-math. I missed that this is unsafe, and there's a fall-back to _muldc3 on NaN. OK, presumably I n

Complex multiply optimization working?

Hi all, I've been looking at implementing the complex multiply patterns for the amdgcn port, but I'm not getting the code I was hoping for. When I try to use the patterns on x86_64 or AArch64 they don't seem to work there either, so is there something wrong with the middle-end? I've tried both

Re: Enable the vectorizer at -O2 for GCC 12

On 31/08/2021 05:13, Jeff Law wrote: On 8/30/2021 9:30 PM, Hongtao Liu via Gcc wrote: On Tue, Aug 31, 2021 at 11:11 AM Kewen.Lin via Gcc wrote: on 2021/8/30 下午10:11, Bill Schmidt wrote: On 8/30/21 8:04 AM, Florian Weimer wrote: There has been a discussion, both off-list and on the gcc-help

Re: Import license issue

On 21/09/2020 12:31, Richard Biener wrote: On Mon, Sep 21, 2020 at 10:55 AM Andrew Stubbs wrote: Ping. Sorry, but you won't get any help resolving license issues from the mailing list. Instead you should eventually ask the SC to "resolve" this issue with the FSF. Agreed,

Re: Import license issue

Ping. On 14/09/2020 17:56, Andrew Stubbs wrote: Hi All, I need to update include/hsa.h to access some newer APIs. The existing file was created by copying from the user manual, thus side-stepping licensing issues, but the updated user manual omits some important details from the APIs I need

Import license issue

Hi All, I need to update include/hsa.h to access some newer APIs. The existing file was created by copying from the user manual, thus side-stepping licensing issues, but the updated user manual omits some important details from the APIs I need (mostly the contents of structs and value of enum

Re: Clobber REG_CC only for some constraint alternatives?

On 20/08/2020 06:40, Senthil Kumar Selvaraj via Gcc wrote: What I didn't understand was the (set-attr "cc") part - as far I can tell, this results in (set_attr "cc_enabled" ...) in all of the three substituted patterns, so I wondered why not just have (set_attr "cc_enabled" ...) in the original d

TImode for BITS_PER_WORD=32 targets

Hi all, I want amdgcn to be able to support int128 types, partly because they might come up in code offloaded from x86_64 code, and partly because libgomp now requires at least some support (amdgcn builds have been failing since yesterday). But, amdgcn has 32-bit registers, and therefore def

Re: How to refine autovectorized loop

On 15/07/2020 03:39, 夏 晋 via Gcc wrote: Hi everyone, I'm trying to autovectorize the loop, and Thank you for the omnipotent macros, everything goes alright. But recently I need to further optimize the loop, I had some problems. As our vector instruction can process 16 numbers at the same

DWARF subregs

Hi all, I'm trying to implement DWARF output for the AMD GCN target, and I've run into trouble; -O0 debug works pretty well, but there are some problems accessing variables in registers. Problem 1 The proposed DWARF specification for the target doesn't specify separate DWARF registers

Re: Please put vim swap files into gitignore

On 18/06/2020 19:20, Thomas Koenig via Gcc wrote: Hi, I just found a few unversioned files called .intrinsic.c.swp and similar in my "git status" output. Could somebody please put .*.swp into .gitignore?  I'm sure this would save at least 10 reverts :-) I have this in my .vimrc to keep such j

Re: GCC 10.1.0 HELP

On 11/06/2020 08:40, MAHDI LOTFI via Gcc wrote: [AMD/ATI] Topaz XT [Radeon R7 M260/M265 / M340/M360 / M440/M445] [1002:6900] (rev 81) I think my GPU is older than fiji and Vega AMDs. Can GCC 10 support my GPU Model? According to Wikipedia (https://en.wikipedia.org/wiki/Radeon_Rx_200_series),

Re: PCH test errors

On 29/05/2020 01:00, Alexandre Oliva wrote: I understand the problem, and I'm tempted to say it was a latent preexisting problem. gcn-hsa.h defines -mlocal-symbol-id=%b in CC1_SPEC. This is a target option not marked as pch_ignore, so option_affects_pch_p returns true for it, and default_pch_va

Re: PCH test errors

On 27/05/2020 15:46, Andrew Stubbs wrote: I'm testing amdgcn-amdhsa, and I get lot of PCH test failures with errors like this: gcc.dg/pch/common-1.c:1:22: error: one or more PCH files were found, but they were invalid gcc.dg/pch/common-1.c:1:22: error: use -Winvalid-pch for more inform

PCH test errors

I'm testing amdgcn-amdhsa, and I get lot of PCH test failures with errors like this: gcc.dg/pch/common-1.c:1:22: error: one or more PCH files were found, but they were invalid gcc.dg/pch/common-1.c:1:22: error: use -Winvalid-pch for more information gcc.dg/pch/common-1.c:1:10: fatal error: com

Re: Blog post about static analyzer in GCC 10

On 26/03/2020 22:30, David Malcolm via Gcc wrote: I wrote a blog post "Static analysis in GCC 10" giving an idea of the current status of the -fanalyzer feature: https://developers.redhat.com/blog/2020/03/26/static-analysis-in-gcc-10/ At some point I'll write up the material for our changes.html

Re: Masked vector deficiencies

On 03/03/2020 15:57, Richard Sandiford wrote: Andrew Stubbs writes: Hi all, Up until now the AMD GCN port has been using exclusively 64-lane vectors with masking for smaller sizes. This works quite well, where it works, but there remain many test cases (and no doubt some real code) that

Masked vector deficiencies

Hi all, Up until now the AMD GCN port has been using exclusively 64-lane vectors with masking for smaller sizes. This works quite well, where it works, but there remain many test cases (and no doubt some real code) that refuse to vectorize because the number of iterations (or SLP equivalent)

Re: Branch instructions that depend on target distance

On 24/02/2020 11:05, Petr Tesarik wrote: Hi all, I'm looking into reviving the efforts to port gcc to VideoCore IV [1]. One issue I've run into is the need to find out target branch distance at compile time. I looked around, and it's not the first one architecture with such requirement, but AFAI

Re: [PATCH, v3] wwwdocs: e-mail subject lines for contributions

On 03/02/2020 18:09, Michael Matz wrote: But suggesting that using the subject line for tagging is recommended can lead to subjects like [PATCH][GCC][Foo][component] Fix foo component bootstrap failure in an e-mail directed to gcc-patc...@gcc.gnu.org (from somewhen last year, where Foo/foo wa

Re: Wrong GCC PR2020 annotated for "[committed, libgomp,amdgcn] Fix plugin-gcn.c bug"

On 23/01/2020 16:46, Joseph Myers wrote: On Thu, 23 Jan 2020, Richard Earnshaw (lists) wrote: Perhaps we should restrict that to a single line, ie only horizontal white space. Our commit style isn't really that free-form when citing bugs. Or perhaps require [:.]?\w after the number (ie an opt

Re: git conversion in progress

On 14/01/2020 13:00, Jonathan Wakely wrote: On Tue, 14 Jan 2020 at 11:37, Georg-Johann Lay wrote: Am 14.01.20 um 12:34 schrieb Andreas Schwab: On Jan 14 2020, Georg-Johann Lay wrote: git clone --reference original-gcc ... Don't use --reference. It is too easy to lose work if you don't kn

Re: [RFC] Characters per line: from punch card (80) to line printer (132)

On 05/12/2019 18:21, Robin Curtis wrote: My IBM Selectric golfball electronic printer only does 90 characters on A4 in portrait mode………(at 10 cps) (as for my all electric TELEX Teleprinter machine !) Is this debate for real ?! - or is this a Christmas spoof ? I can't speak for the debate, b

Re: [RFC] Characters per line: from punch card (80) to line printer (132)

On 05/12/2019 16:17, Joseph Myers wrote: Longer lines mean less space for multiple terminal / editor windows side-by-side to look at different pieces of code. I don't think that's an improvement. Here's a data-point My 1920 pixel-wide screen, in the default font, allows 239 columns; not

Re: RTL alternative selection question

On 23/09/2019 15:39, Andrew Stubbs wrote: On 23/09/2019 15:15, Segher Boessenkool wrote: On Mon, Sep 23, 2019 at 11:56:27AM +0100, Andrew Stubbs wrote:    [(set (match_operand:DI 0 "register_operand"  "=Sg,v") (ashift:DI    (match_operand:DI 1 &quo

Re: RTL alternative selection question

On 23/09/2019 16:21, Segher Boessenkool wrote: Pass the register class or constraint or something like that to the hook, then based on what the hook returns, either or not do the reject? So your hook would special-case SCC_CONDITIONAL_REG, maybe a few more similar ones (those are confusing names

Re: RTL alternative selection question

On 23/09/2019 15:15, Segher Boessenkool wrote: On Mon, Sep 23, 2019 at 11:56:27AM +0100, Andrew Stubbs wrote: [(set (match_operand:DI 0 "register_operand" "=Sg,v") (ashift:DI (match_operand:DI 1 "gcn_alu_operand" " Sg,v")

RTL alternative selection question

Hi All, I'm trying to figure out how to prevent LRA selecting alternatives that result in values being copied from A to B for one instruction, and then immediately back from B to A again, when there are apparently more sensible alternatives available. I have an insn with the following patter

Re: New jump threading issue

On 07/12/2018 22:41, Segher Boessenkool wrote: On Fri, Dec 07, 2018 at 05:57:39PM +, Andrew Stubbs wrote: Since the postreload_jump pass was added I'm having trouble with the AMD GCN port. [ snip a lot ] It seems thread_jump does not notice your scc in its "nonequal" regse

New jump threading issue

Since the postreload_jump pass was added I'm having trouble with the AMD GCN port. I have the following, after reload (RTL slightly simplified!): (insn (set (reg scc) (gtu (reg s26) (reg s25 (jump_insn (set pc (if_then_else (ne scc 0)) (label_ref 46) pc))) . (insn (set (reg scc) (eq (re

define_subst question

I want to use define_subst like this: (define_subst "vec_merge_with_vcc" [(set (match_operand 0) (match_operand 1)) (set (match_operand 2) (match_operand 3))] "" [(parallel [(set (match_dup 0) (vec_merge (match_dup 1) (match_opera

Should "can_create_pseudo_p" check "lra_in_progress"?

I just tracked down a "reload" bug and was very surprised to find that can_create_pseudo_p doesn't return false during register allocation when using LRA. It's still defined like this: #define can_create_pseudo_p() (!reload_in_progress && !reload_completed) Is it deliberate that it doesn't ch

Re: DSE and maskstore trouble

On 03/07/18 14:52, Richard Biener wrote: If you look at RTL dumps (with -fstrict-aliasing, thus -O2+) you should see MEM_ALIAS_SETs differing for the earlier stores and the masked store uses. Now I'm of course assuming DSE is perfect, maybe it isn't ... ;) Ok, I see that the stores have MEMs w

Re: DSE and maskstore trouble

On 03/07/18 13:21, Richard Biener wrote: Ok, so if we vectorize the above with 64 element masked stores then indeed the RTL representation is _not_ safe. That is because while the uses in the masked stores should prevent things from going bad there is also TBAA to consider which means those uses

Re: DSE and maskstore trouble

On 03/07/18 12:45, Richard Biener wrote: On Tue, Jul 3, 2018 at 1:38 PM Andrew Stubbs wrote: On 03/07/18 12:30, Richard Biener wrote: Hmm, so they're safe, but may prevent the optimization of nearby variables? Yes, they prevent earlier stores into lanes that are "really" w

Re: DSE and maskstore trouble

On 03/07/18 12:30, Richard Biener wrote: Hmm, so they're safe, but may prevent the optimization of nearby variables? Yes, they prevent earlier stores into lanes that are "really" written to to be DSEd. Right, but I have unrelated variables allocated to the stack within the "shadow" of the ma

Re: DSE and maskstore trouble

On 03/07/18 12:02, Richard Biener wrote: I believe that the AVX variants like (define_expand "maskstore" [(set (match_operand:V48_AVX512VL 0 "memory_operand") (vec_merge:V48_AVX512VL (match_operand:V48_AVX512VL 1 "register_operand") (match_dup 0) (mat

Re: DSE and maskstore trouble

On 03/07/18 11:33, Andrew Stubbs wrote: On 03/07/18 11:15, Richard Biener wrote: AVX ones are all UNSPECs I believe - how do your patterns look like? AVX has both unspec and vec_merge variants (at least for define_expand, in GCC8), but in any case, AFAICT dse.c only cares about the

Re: DSE and maskstore trouble

On 03/07/18 11:15, Richard Biener wrote: AVX ones are all UNSPECs I believe - how do your patterns look like? AVX has both unspec and vec_merge variants (at least for define_expand, in GCC8), but in any case, AFAICT dse.c only cares about the destination MEM, and all the AVX and SVE patterns

DSE and maskstore trouble

Hi All, I'm trying to implement maskload/maskstore for AMD GCN, which has up-to 64-lane, 512-byte fully-masked vectors. All seems fine as far as the vector operations themselves go, but I've found a problem with the RTL Dead Store Elimination pass. Testcase gcc.c-torture/execute/20050826-2.c

Re: Vector pointer modes

On 16/05/18 22:01, Richard Sandiford wrote: Andrew Stubbs writes: Hi all, I'm in the process of trying to update our AMD GCN port from GCC 7 to GCC 8+, but I've hit a problem ... It seems there's a new assumption that pointers and addresses will be scalar, but GCN load instr

Re: Vector pointer modes

On 16/05/18 17:24, Richard Biener wrote: On May 16, 2018 6:03:35 PM GMT+02:00, Andrew Stubbs wrote: Is there a new way of dealing with vectors of pointers? Maybe you can masquerade it behind a large scalar integer mode?... We're using V64DImode to represent a vector of 64 64-bit poi

Vector pointer modes

Hi all, I'm in the process of trying to update our AMD GCN port from GCC 7 to GCC 8+, but I've hit a problem ... It seems there's a new assumption that pointers and addresses will be scalar, but GCN load instructions require vectors of pointers. Basically, machine_mode has been replaced with

Re: AMD GCN port

On 11/05/18 12:18, Andrew Stubbs wrote: The other thing that's occurred to me is that with og8 being new, maybe it's a good time to merge the GCN stuff into that, and work with the NVidia folks to share it. [Adding Cesar and Thomas to CC.] I'm aware of some incompatibilitie

Re: AMD GCN port

On 11/05/18 10:26, Richard Biener wrote: Sounds good but I'd not do 1. given the github repo can serve as archiving point, too. Having 2. doesn't sound too useful over 3. so in the end I'd do only 3. and 4. Of course 1 and 2 might help you in doing 3 and 4. Indeed, I've been worried that I'm

AMD GCN port

\ / | | gcn-openacc-8-branch | |\ ,-' | gcn |/ gcc-9 It's slightly complex to describe, but hopefully logical and workable. Comments? Better suggestions? -- Andrew Stubbs Mentor Graphics / CodeSourcery.

Re: Register allocation trouble

On 24/07/17 14:58, Georg-Johann Lay wrote: Dunno if that works in all situation. For example, when the register allocator is facing high register pressure and decides to spill the target register, it uses the constraints of the matched insn. That would be a memory to memory move, and therefore

Re: Register allocation trouble

Thanks to all those who replied. :-) Here's what I've done to fix the problem: 1. Set the base rclass to A only. 2. Configured secondary reloads to B via A. 3. Disabled the Rb constraint. [*] That's enough to create correct code, but it's pretty horrible, so I also added new patterns of the

Register allocation trouble

Hi all, I have an architecture that has two register files. Let's call them class A and class B. There are some differences between their capabilities, but for the purposes of this problem, they can be considered to be identical, both holding SImode values, and both able to receive values wit

32-bit build failure

Hi Martin, It looks like your change r242000 broke builds on 32-bit hosts: fold-const-call.c:1541:36: error: cannot convert 'size_t* {aka unsigned int*}' to 'long long unsigned int*' for argument '2' to 'const char* c_getstr(tree, long long unsigned int*)' Basically, the code only works wher

Re: Help with reload bug, please

On 23/01/15 16:34, Jeff Law wrote: Just for reference, the PA allows a 14 bit displacement in memory addresses which use integer registers, but only a 5 bit displacement for FP registers. Other than the displacement amounts, I suspect this is the same core problem you have on your port. Yes, t

Help with reload bug, please

How does reload ensure that an SImode value (re)loaded into an FP register has a valid stack index? The FP load instruction allows a smaller index range than the integer equivalent, but nothing checks the destination register, only the source mode. I'm trying to solve a problem in which GCC

Re: Why does lower-subreg mark copied pseudos as "decomposable"?

On 19/04/12 17:36, Andrew Stubbs wrote: On 18/04/12 21:47, Richard Sandiford wrote: I still prefer the idea of disabling in the first pass. It'll need to be tested on something like non-NEON ARM to see whether it makes things worse or better there. (I think size testing would be fine.)

Re: Why does lower-subreg mark copied pseudos as "decomposable"?

On 18/04/12 21:47, Richard Sandiford wrote: I don't think the idea is that these cases are special in themselves. What we're looking for are pseudos that _may_ be decomposed into separate registers. If one of the pseudos in the move is only used in decomposable contexts (including nonvolatile lo

Re: Why does lower-subreg mark copied pseudos as "decomposable"?

On 18/04/12 16:53, Richard Sandiford wrote: Andrew Stubbs writes: On 18/04/12 11:55, Richard Sandiford wrote: The problem is that not all register moves are always going to be eliminated, even when no mode changes are involved. It might make sense to restrict that code you quoted

Re: Why does lower-subreg mark copied pseudos as "decomposable"?

On 18/04/12 11:55, Richard Sandiford wrote: The problem is that not all register moves are always going to be eliminated, even when no mode changes are involved. It might make sense to restrict that code you quoted: case SIMPLE_PSEUDO_REG_MOVE: if (MODES_TIEABLE_P (GET

Re: Why does lower-subreg mark copied pseudos as "decomposable"?

On 17/04/12 18:20, Richard Sandiford wrote: Andrew Stubbs writes: Hi all, I can see why copying from one pseudo-register to another would not be a reason *not* to decompose a register, but I don't understand why this is a reason to say it *should* be decomposed. The idea is that,

Why does lower-subreg mark copied pseudos as "decomposable"?

Hi all, I can see why copying from one pseudo-register to another would not be a reason *not* to decompose a register, but I don't understand why this is a reason to say it *should* be decomposed. This is causing me trouble, and I can't tell how to fix it without figuring out why it is this

Re: Syncing with Launchpad Bug Tracker

On 27/04/11 18:29, Deryck Hodge wrote: I work at Canonical on Launchpad and am trying to setup syncing between our bug tracker and the GCC bug tracker. Specifically, we want to enable comment syncing between linked bugs on our trackers and back links from your Bugzilla to the Launchpad bug. Cur

Re: running GCC without any input files, but with plugins???

On 08/04/11 07:04, Basile Starynkevitch wrote: So I am dreaming of a way to run gcc with cc1 but without input files. Perhaps something like gcc -fplugin=foo.so -fplugin-arg-foo-bar=bee -frun-cc1-without-input gcc -fplugin=foo.so -fplugin-arg-foo-bar=bee -x c /dev/null Andrew

Re: Triplet for ARM Linux HardFP ABI, again

On 21/02/11 10:12, Guillem Jover wrote: This was already discussed in this list some time ago [0]. But it came up again when restarting the discussion for the proposed new armhf port for Debian. [0] My arguments for why a distinct triplet is n

Re: combine two load insns

On 08/12/10 14:39, Jeff Law wrote: >> Sorry, I think I wasn't clear. I didn't mean constraints in term on >> RTL template constraints, but 'constraints' coming from the new DI >> destination of the load. More specifically: 2 SI loads can target >> totally independent registers whereas a standard D

Re: define_split

On 09/11/10 22:54, Michael Meissner wrote: The split pass would then break this back into three insns: (insn ... (set (reg:SF ACC_REGISTER) (mult:SF (reg:SF 124) (reg:SF 125 (insn ... (set (reg:SF ACC_REGISTER)

Re: Triplet for ARM Linux HardFP ABI

On 12/07/10 14:25, Andrew Stubbs wrote: This means that we need to choose a name for it. Obviously, it's better if it's an "official" name, so I want to discuss it here. I'm aware that there is some bikeshedding to do here, but it's better it gets done before any

Re: Triplet for ARM Linux HardFP ABI

On 12/07/10 15:51, Richard Earnshaw wrote: if we could turn back the clock, I'd even prefer arm-linux_gnu_hf_eabi to get back to a single '-'-parsed OS string, but the linux-gnu stuff is now entrenched, so trying to change back would only cause more disruption. quadruplets, quintuplets and eve

Triplet for ARM Linux HardFP ABI

ething of a hack to me. FAOD, the new triplet would only set the default ABI variant. This can already be achieved via configure options, so this adds no real new functionality. This is just about agreeing how to label it. Andrew Stubbs CodeSourcery (currently working with Linaro)

Re: [SH] ICE compiling pr34330 testcase for sh-linux-gnu

On 09/07/09 19:11, Ian Lance Taylor wrote: Andrew Stubbs writes: The problem insn is created by gen_reload when it is given the following rtl as input: (plus:SI (plus:SI (reg/v/f:SI 4 r4 [orig:192 a ] [192]) (const_int 2 [0x2])) (reg:SI 0 r0 [orig:188 ivtmp.24 ] [188])) You

[SH] ICE compiling pr34330 testcase for sh-linux-gnu

I'm having trouble with an ICE, and I'm hoping somebody can enlighten me. Given the following command: cc1 -fpreprocessed ../pr34330.i -quiet -dumpbase pr34330.c -da -mb -auxbase-strip pr34330.c -Os -version -ftree-parallelize-loops=4 -ftree-vectorize -o pr34330.s -fschedule-insns I get an i

Re: Aliasing bug

On 02/07/09 14:34, Richard Guenther wrote: No, that's invalid. You would have to do extern union { void *foo; short *bar; }; using the union for the double-indirect pointer doesn't help. Or simply use memcpy to store to foo. Ah, I did not know that. I still don't understand how a refe

Re: Aliasing bug

On 02/07/09 14:26, Richard Guenther wrote: You are writing to memory of type void * via an lvalue of type short *. Yes, there is type punning there, but that should work, shouldn't it? This code is distilled from some glibc code I'm having trouble with. Andrew

Aliasing bug

Hi all, I'm fairly sure I have found an aliasing bug in GCC, although I could be wrong. I've reproduced it in both 4.4 and mainline. Consider this testcase, aliasing.c: extern void *foo; extern inline short ** f1 (void) { union { void **v; sh

Re: gcc-get enabling-only subscription?

Joern Rennecke wrote: You could sub up to the digest mode, which might at least be less of a burden, It would reduce the number of messages, but the volume would still be very high. Hi Joern, You could just sign up to one of the online mail list services. Here's the nabble link for this

Re: Libmudflap for sh-elf toolchain cannot access environment variable MUDFLAP_OPTIONS

Deepen Mantri wrote: We cannot place putenv("MUDFLAP_OPTIONS=<..>") in libmudflap's __mf_init() function existing in mf-runtime.c. Placing putenv(..) will limit the instrumented code's runtime behaviour only to option being set in the code by me. Well no, that would be silly - you might as wel

Re: Libmudflap for sh-elf toolchain cannot access environment variable MUDFLAP_OPTIONS

Deepen Mantri wrote: How to make x86/linux shell's environment variable (MUDFLAP_OPTIONS) accessible to test.out while executing it through the sh-elf simulator? I don't know about other targets, but the SH newlib/crt/simulator doesn't do anything with the environment. You could spend ages

Subversion access via http proxy

go back a few versions now. Is there any equivalent for the new gcc.gnu.org repository? I tried anoncvs and anonsvn, among others. If so could somebody put it on the wiki. Thanks. Andrew Stubbs P.S. The wiki page seems to have got a little confused. It used to have three different examples

RE: Accessing the subversion repository

port it but I can't easily test that assumption because I don't have 3.9 locally either. Thanks anyway -- Andrew Stubbs

RE: Accessing the subversion repository

> > > I should note that svn treats it's remote connections as > > > disposable, so > > > svn+ssh will probably connect more than once for things > like remote > > > diffs. So if it takes a while to authenticate, this may > not be your > > > best bet if you are looking for blazing speed (as som

RE: Accessing the subversion repository

d something somewhere. Anyway, I can live with it for the moment. Thanks a lot. -- Andrew Stubbs [EMAIL PROTECTED]

Accessing the subversion repository

gnu.org, is there any plans to support the alternative protocols? Thanks -- Andrew Stubbs [EMAIL PROTECTED]