On 17/10/2024 16:51, Richard Sandiford wrote:
> Ramana Radhakrishnan via Gcc writes:
> > I am pleased to announce that the GCC Steering Committee has appointed
> > Alex Coplan as a maintainer for the AArch64 load / store pair fusion
> > pass.
> >
> > In additio
.2086163002
107 : 99.2086163002
108 : 99.2086163002
I was just wondering if anyone knows what the rationale for this behaviour is,
and can point to the relevant bit in the source?
I can imagine it might be something to do with floating-point precision
and not wanting probabilities to get too small or large, but I'm not
sure.
Thanks,
Alex
Hi,
These instructions looks to be part of the T-head vendor extension instruction
set. With the spec here https://github.com/T-head-Semi/thead-extension-spec.
Best regards
Alex
> On Jan 23, 2024, at 8:42 AM, jacob navia via Gcc wrote:
>
> Hi
> The GNU assembler supports two
eed different, don't you
think? The easiest solution is for the standard to just declare this
outlaw, IMO.
Maybe it could do an exception for printing, that is, reading a pointer
is not a problem in itself, a long as you don't compare it, but I'm
Hi Martin,
On 2/23/23 20:57, Martin Uecker wrote:
Am Donnerstag, dem 23.02.2023 um 20:23 +0100 schrieb Alex Colomar:
Hi Martin,
On 2/17/23 14:48, Martin Uecker wrote:
This new wording doesn't even allow one to use memcmp(3);
just reading the pointer value, however you do it, is UB.
m
It's rather unspecified behavior. Still
unpredictable: (memcmp(&p, &p, sizeof(p) == 0) might evaluate to true or
false randomly; the compiler may compile out the call to memcmp(3),
since it knows it won't produce any observable behavior.
<https://software.codidact.com/po
}
}
This would in fact deprecate plain `struct sockaddr`, as Bastien suggested.
Cheers,
Alex
--
<http://www.alejandro-colomar.es/>
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Hi Rick,
On 1/24/23 12:16, Rich Felker wrote:
On Fri, Jan 20, 2023 at 12:06:50PM +0200, Stefan Puiu via Libc-alpha wrote:
Hi Alex,
On Thu, Jan 19, 2023 at 4:14 PM Alejandro Colomar
wrote:
Hi!
I just received a report about struct sockaddr_storage in the man pages. It
reminded me of some
ion about a fix.
Thanks.
And, with LTO TU boundaries are lost, inlining or other IPA optimizations
(including say modref) work in between TUs.
Yeah, that's why we need a fix. Compilers will only get better at
optimizing, so UB will sooner or later be a problem.
Cheers,
Alex
--
<http://w
ge can be reconverted
to that purpose.
Cheers,
Alex
--
<http://www.alejandro-colomar.es/>
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On 11/29/22 18:19, Alex Colomar wrote:
Hi Martin, Joseph,
On 11/29/22 18:00, Martin Uecker wrote:
Am Dienstag, dem 29.11.2022 um 16:53 + schrieb Jonathan Wakely:
On Tue, 29 Nov 2022 at 16:49, Joseph Myers wrote:
On Tue, 29 Nov 2022, Michael Matz via Gcc wrote:
like. But I'm gene
rr[i] = i;
}
void bar(int arr[])
{
// Constraint violation
for (size_t i = 0; i < _Nitems(arr); i++)
arr[i] = i;
}
This is probably the most useful part of this feature (but admittedly
it's not only about this feature, or even could be added without this
ich was my first draft) would
have probably been the source of hidden bugs, since it might work (read
compile) in some cases, but with wrong results.
I prefer this hypothetical syntax, which at most will cause compile errors.
Cheers,
Alex
Martin
--
<http://www.alejand
size_t conversion would disallow that syntax.
Yes, this then does not work.
Cheers,
Alex
--
<http://www.alejandro-colomar.es/>
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zm@illithid/T/#m794ad2a3173a19099625ee1dec7ea11ab754513d>
I don't have his email address (I don't see any emails from him on the
reflector since I joined it in 2001).
Meh; thanks. Would you mind commenting this issue to whoever defends
his document, whenever you talk about it?
T
ver), and letting ISO C / GCC
implement initially (and possibly ever) only the minimal stuff.
And even when they are, many issues
may well arise in practice (see the long list of constexpr issues in my
commit message for that C2x feature, for example, which I expect to turn
into multiple N
build go green again here?
Thanks,
Alex
mailing lists
>instead of directly to me. I'm not the only person that knows how to
>answer these kinds of questions, and I don't always have time to help
>everyone myself. I'd like to spread the load around if possible.
>
>Jim
Kind regards Alex Hill.
--
Kind regards Alex Hill.
On 18/08/15 10:45, Marcus Shawcroft wrote:
On 18 August 2015 at 10:25, Alex Velenko wrote:
On 31/07/15 12:04, Alex Velenko wrote:
On 29/07/15 23:14, Jeff Law wrote:
On 07/28/2015 12:18 PM, Alex Velenko wrote:
On 21/04/15 06:27, Jeff Law wrote:
On 04/20/2015 01:09 AM, Shiva Chen
On 31/07/15 12:04, Alex Velenko wrote:
On 29/07/15 23:14, Jeff Law wrote:
On 07/28/2015 12:18 PM, Alex Velenko wrote:
On 21/04/15 06:27, Jeff Law wrote:
On 04/20/2015 01:09 AM, Shiva Chen wrote:
Hi, Jeff
Thanks for your advice.
can_replace_by.patch is the new patch to handle both cases
On 29/07/15 23:14, Jeff Law wrote:
On 07/28/2015 12:18 PM, Alex Velenko wrote:
On 21/04/15 06:27, Jeff Law wrote:
On 04/20/2015 01:09 AM, Shiva Chen wrote:
Hi, Jeff
Thanks for your advice.
can_replace_by.patch is the new patch to handle both cases.
pr43920-2.c.244r.jump2.ori is the
ff
Hi,
I see this patch been committed in r56 on trunk. Is it okay to port
this to fsf-5?
Kind regards,
Alex
ding of situation and the example is UB?
* if two definitions had the same fields and the same constructors,
should the program be correct?
* is correct gcc behaviour with `-O1' a coincidence, or it detects
another class anyway?
* does it make sense to give a warning in that case?
Kind regards,
Markin Alex
ent compilation
units. The C++ One Definition Rule is used.
* It can be used to strengthen unreachable function removal.
* Feedback-directed devirtualization was extended in GCC 4.9 to work
inter-module with LTO.
Alex
ded. I've just added a configure-time warning for 4.6, though, as
that's about all I can affect, from within a plugin source tree.
Thanks again,
Alex
led with 4.6?
Kind regards,
Alex
tdc++. Only four
of the tests fail; further digging led me to figure out that missing
`all_decls` is a much bigger problem than I'd initially thought..
Any help, pointers or advice would be really, really appreciated! If /
when it's up to standard, I'd like to propose it for in
ng to the issue 6.5 (7), we cat access to an object value
with expression that has
> a qualified version of a type compatible with the effective type of the object
So, `const int *' can legally point to the `int *' but not in reverse
order, and that's why `const int *' and `int *' should be in different
alias sets?
Alex.
not able to handle such situation... or perhaps there is
something which prevents the modulo scheduler from arriving to this situation?
Alex
--- On Thu, 7/19/12, Andrey Belevantsev wrote:
> From: Andrey Belevantsev
> Subject: Re: SMS issues
> To: "Alex Turjan"
> Cc: g
ove.
regards,
Alex
I applied the new patch and it seams fine.
Thanks!
Alex
--- On Wed, 7/18/12, Alexander Monakov wrote:
> From: Alexander Monakov
> Subject: Re: selective scheduler failure
> To: "Alex Turjan"
> Cc: "Alexander Monakov" , gcc@gcc.gnu.org
> Date: Wednesday, J
I found the patch from the following link:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52250
But i dont see the removal of the assert in move_bb_info.
Perhaps you have another patch related to this bug.
thanks
Alex
--- On Tue, 7/17/12, Alexander Monakov wrote:
> From: Alexander Mona
Hi,
I tried the patch but it doesnt solve my problem.
The patch addresses the problem on the else branch but my problem is on the if:
if (can_merge_blocks_p (bb->prev_bb, bb))
sel_merge_blocks ...
Alex
--- On Tue, 7/17/12, Alexander Monakov wrote:
> From: Alexander Monakov
> Su
region_p (bb->prev_bb))
I added this description to buggzila under Bug 53999.
regards,
Alex
On Thu, 2012-03-08 at 08:13 +0100, Ingo Molnar wrote:
> * Alex Shi wrote:
>
> > On Wed, 2012-03-07 at 14:39 +0100, Ingo Molnar wrote:
> > > * Alex Shi wrote:
> > >
> > > > > I think the check should be (__alignof__(lock) <
> > > >
> > 1, it is alignof bug for default gcc on my fc15 and Ubuntu 11.10 etc?
> >
> > struct sub {
> > int raw_lock;
> > char a;
> > };
> > struct foo {
> > struct sub z;
> > int slk;
> > char y;
> > }__attribute__((packed));
> >
> > struct foo f1;
> >
> > __
On Wed, 2012-03-07 at 14:39 +0100, Ingo Molnar wrote:
> * Alex Shi wrote:
>
> > > I think the check should be (__alignof__(lock) <
> > > __alignof__(rwlock_t)), otherwise it will still pass when
> > > you have structure with attribute((packed,aligned(2)))
&g
> I think the check should be (__alignof__(lock) < __alignof__(rwlock_t)),
> otherwise it will still pass when you have structure with
> attribute((packed,aligned(2)))
reasonable!
>
>> 1, it is alignof bug for default gcc on my fc15 and Ubuntu 11.10 etc?
>>
>> struct sub {
>> int raw
On Tue, 2012-03-06 at 09:32 +, Arnd Bergmann wrote:
> On Tuesday 06 March 2012, Alex Shi wrote:
> > I have one concern and one questions here:
> > concern: maybe the lock is in a well designed 'packed' struct, and it is
> > safe for cross lines issue
, and if needs be, I have several x32 and x64 macs I can test things on.
--
Alex J Avriette
http://search.cpan.org/~alex/
http://www.linkedin.com/in/avriette (+1 858 3677293)
ange thing is that only certain symbols from are unresolved. Other
symbols from the same libraries are there.
Can anyone shed some light on how the linker generate the shared/static
libraries and why some libraries are not linked while some are, even
when they are all available from the same location.
Alex
If I understood correct, gcc could replace insns 5, 7, 8 and 9 by the
insn defined as "*and_2", but it seems "combine" did not tried that.
How gcc could perform such optimization (and similar ones) ? Is a
peephole the most indicated to do
the current cycle). Thus the best insn reservation makes possible scheduling
antidependent insns of cost zero in the same cycle by avoiding resource
conflicts.
Alex
few changes in the gcc mainline sources
--- On Fri, 2/11/11, Bernd Schmidt wrote:
> From: Bernd Schmidt
> S
Alexander is right. Perhaps you can implement the TARGET_SCHED_ADJUST_COST
, then catch in the debugger the two instructions that you expect to be
scheduled together and see what the default latency is or if needed you
may just adjust it to the proper value.
Alex
--- On Fri, 11/12/10
and
then (in case)
unschedule INSN.
thanks,
Alex
Hi Jeff,
Thanks for answer. I managed to make use of an architecture trick which allows
me to get the secondary reload via only one intermediary register, but still
have some comments to what you wrote me.
> > 1.Is it possible to do the secondary reload via 2
> intermediary registers?
> > As far
get reloaded as well? and if yes how?
thanks in advance,
Alex
Hi,
Is there functionality in gcc based on which the CFG can be traversed in such a
way that a node gets visited once all of its predecessors have been visited?
thanks,
Alex
> insns which branch are not allowed to have output
> reloads. You must
> support any kind of register as well as memory operands in
> your insn for
> the loop counter.
Thanks for answer but what do you suggest to do, as my architecture done not
support HW loops with memory operands?
Alex
t; 183)
lib5.c:105:1: internal compiler error: in find_reloads, at reload.c:3821
Can anybody give me a hint?
I am aware of the following msg:
http://gcc.gnu.org/ml/gcc/2001-09/msg00942.html
but still dont know how to make reload do the work.
thanks,
Alex
> Do I have to reorganize the code prior to slot filling? Do
> I have to make sure that some problematic instructions do
> not appear in slots?
Perhaps a easy way to solve the problem would be to claim for branches a memory
port a number of stages before and after the IF; to avoid in this way ha
Im writing to you regarding a possible bug in linear loop transfor.
The bug can be reproduce by compiling the attached c file with gcc.4.5.0
(20100204, 20100325) on x86 machine.
The compiler flags that reproduce the error are:
-O2 -fno-inline -fno-tree-ch -ftree-loop-linear
If the compiler is ru
t;) b>) [0 b+0 S2 A16])
(mem/i:HI (symbol_ref:HI ("a") [flags 0x2] 0x7fdad430 a>) [0 a+0 S2 A16]))) -1 (nil)
(nil))
I understood that gcc would like to have a insn which accepts "reg =
mem + mem", but I really can not understand why gcc works OK with -O2
and with -O0, but not with -O1.
thank you!
Alex Prado
operands of the
"mulsi3" instruction as defined by the define_expand construct. In this way
instead of the two separate HI loads (from my previouse mail) I get only one SI
load which aliases whith the SI store. In consequence the SI store is no longer
removed.
1.What do you think about this implementation? using define_insn_and_split
2.Is is true that in the define_expand constructs I should avoid inducing
subregs?
thanks,
Alex
ot treated properly by dse?
I observed that if I run with the flag -fno-strict-aliasing the wrongly removed
store is no longer removed and the code is runs correctly.
Im wondering does the dse after register allocation make use of type based
alias analysis?
reagards,
Alex
> With 4.4, IRA happens to reuse the same register for both pseudos, so
> sched2 is hand tied and cannot schedule them back again for us.
I can imagine compiling other programs for which preserving the 4.3 allocation
will induce performance degradation due to spilling.
The register allocator t
> Gcc only does this work in the second pass, but what's the
> point? Is it wrong or just not necessary in the first sched
> pass?
Regardless of the target architecture from the correctness point of view sched1
can be disabled. sched1 has as purpose shortening live ranges.
Short live ranges allo
I download source code for book >
from:http://users.cs.fiu.edu/~weiss/dsaa_c++/code/,try to compiler
it,but got many errors,most of them say:
.. previously declared here
...: redefinition of .
I think template causes these erro
set by asrl if the result is 0,
so "tstl %d0" is not necessary, right ?
In 68020 the result is the same, but I could not find the 680x0 RM manual.
thank you,
Alex Prado
--- On Thu, 5/7/09, Maxim Kuvyrkov wrote:
> From: Maxim Kuvyrkov
> Subject: Re: scheduling question
> To: atur...@yahoo.com
> Cc: "Vladimir Makarov" , gcc@gcc.gnu.org
> Date: Thursday, May 7, 2009, 1:01 PM
> Alex Turjan wrote:
> > Hi,
> > During schedu
Hi,
During scheduling Im confronted with the fact that an instruction is moved
from the ready list to queued with the cost 2, while according to my
expectations the insn should have been moved to queued with cost 1.
Did anybody experience similar problem?
In case an insn is ready but can bot be
> For data dependency cases, I do some jobs in
> the adjust_cost target hook.
Normally the scheduling takes into account the instruction latencies which you
have specified: for load 2, for mul 4 and for alu 1.
Why do you need to adjust the sched costs? Did you try simply without adjusting
the c
Are there any plans to move the partial unrolling phase from
RTL to Tree-SSA?
The move would benefit from better (or easier to implement) Tree-SSA alias
analysis.
Alex
>
>
>
>
> --- On Wed, 4/22/09, Li Feng
> wrote:
>
> > From: Li Feng
> > Subject: [
>= dfa_insn_codes_length)
dfa_insn_code_enlarge (uid);
dfa_insn_codes[uid] = internal_dfa_insn_code (insn_code_move_fake1);
In this way when the scheduler calls internal_state_transition, the ready
instruction has been already set its dfa_insn_codes to a unit reservation
schedulable in the current s
Which does not seem true to me.
Is there a way for automatons to communicate so that the alternative
(unit1_aut1, unit2_aut2) would be rejected?
regards,
Alex
Hello,
Some time ago I asked a question regarding the possibility to schedule an
operation on alternative functional units (FUs) AND depending on the chosen FUs
to generate a dedicated assembly mnemonic.
To give a simple example suppose I have a move operation that can be issued on
one of the
can I decide which of the two alternatives
(c_valu_1 or c_vlsu_1) the scheduler has selected?
thanks for your help!
Alex
> Keep
> track of the instruction slot, and set some global variable
> in that macro.
I see what you mean but for my target architecture the slots are not
identical in sense that they are claiming totaly different resources.
This means that in order to decide at a certain cycle which mnemonic
return "add-slot1, %0, %1, %2";
> }
> }
> [(set_attr "type" "alu")
>(set_attr "mode" "SI")
>(set_attr "length" "1")])
>
> > -Original Message-
> > From: [EMAIL PROTECT
" "1")])
On my target machine "alu" is a reservation that occupies one of the following
3 slots: "slot1|slot2|slot3" and, I need to generate assembly code with
different mnemonic depending on which slot the instruction was scheduled:
add-slot1 %0,%1,%2% // if scheduled on slot 1
add-slot2 %0,%1,%2% // if scheduled on slot 2
add-slot3 %0,%1,%2% // if scheduled on slot 3
Alex
Hello,
I noticed I miss few important things in the first email regarding
mirror.
Mirror name: gcc.releasenotes.org
Mirror url: http://gcc.releasenotes.org
Location: USA, TX
Supporter: [EMAIL PROTECTED]
I hope all fine now.
Thnaks.
Alex Korolev
[EMAIL PROTECTED]
Hello,
Karl Berry (GNU webmaster) ask me contact with you about new GCC mirror.
It's up already. Please check http://gcc.releasenotes.org/
Let me know if you need something else.
Thanks.
Alex Korolev
[EMAIL PROTECTED]
where you have RTL instructions)
is caught with the
with something like this:
(INSN_P(insn) && recog_memoized(insn) ==
CODE_FOR_customop_unroll_pragma
more or less this is it.
Alex
--- Bingfeng Mei <[EMAIL PROTECTED]> wrote:
> Alex, Thanks for your suggestion. What target hook
&
unroll intrinsics.
hope this will help,
Alex
of an article by Sanjiv Gupta and Naveen
Sharma on alias analysis at the RTL level, which was
published in the GCC 2003 summit. Are there any
further gcc developments of this work or is there a
patch concerning this work?
thanks in advance,
Alex Turjan
his will cause gcc to pad this entry
out to ensure that it starts on an 8 byte boundary.
Does this make sense?
Alex
On 8/9/07, Alex Gonzalez <[EMAIL PROTECTED]> wrote:
> Hi,
>
> I'll try to come up with a short test.
>
> I have narrowed it a bit more. The PVAR structure
esn't happen.
Also, if I do
static void varcopy(void *pvar1, void *pvar2)
the compiler uses sdl and avoids the crash.
I am compiling for n32 ABI, so the register size is 64bits.
Any ideas?
On 8/9/07, David Daney <[EMAIL PROTECTED]> wrote:
> Alex Gonzalez wrote:
> > Hi,
>
) 3.3-mips64linux-031001
Has anyone experienced this problem before?
Regards,
Alex
---
For reference,
The resulting code without optimizing is:
81024534 :
varcopy():
81024534:27bdffd0 addiusp,sp,-48
81024538:ffbf0020 sd
show_bug.cgi?id=25351 and another one which
I can't remember :)
I don't see any progress on GCOV, so I assume it's up to me to fix these
bugs. I'm writing here to cooperate with GCOV developers to avoid
duplicate work.
--
With respect,
Alex Besogonov ([EMAIL PROTECTED])
Dear developers,
I have recently upgraded my PC to Suse Linux 10 (from 9.3). The
distribution
comes with gcc 4.0.2. The problem that arrised after the upgrade is that
I
cannot compile f77 codes anymore. More precisely when I try to compile a
Fortran file (*.f) I am getting the error:
"gcc: inst
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