Snapshot gcc-9-20200911 is now available on
https://gcc.gnu.org/pub/gcc/snapshots/9-20200911/
and on various mirrors, see http://gcc.gnu.org/mirrors.html for details.
This snapshot has been generated from the GCC 9 git branch
with the following options: git://gcc.gnu.org/git/gcc.git branch
On Fri, Sep 11, 2020 at 4:36 PM Janne Blomqvist
wrote:
> On Fri, Sep 11, 2020 at 6:52 PM Joel Sherrill wrote:
> >
> > Hi
> >
> > Over at RTEMS, we ran into a case where the C++ atomics may not be right
> > for one of the lower level x86 models. We will investigate whether it can
> > be made righ
On Fri, Sep 11, 2020 at 6:52 PM Joel Sherrill wrote:
>
> Hi
>
> Over at RTEMS, we ran into a case where the C++ atomics may not be right
> for one of the lower level x86 models. We will investigate whether it can
> be made right but this has led to the discussion of dropping older models
> and set
On Fri, Sep 11, 2020 at 1:40 PM Florian Weimer wrote:
> * Joel Sherrill:
>
> > I don't know that we have a huge issue in making the i486 a minimum.
> > I was proposing a Pentium II or P6 as a baseline since that moves you
> > up to having a TBR and initial SMP support.
>
> Sorry, what's a TBR?
>
* Joel Sherrill:
> I don't know that we have a huge issue in making the i486 a minimum.
> I was proposing a Pentium II or P6 as a baseline since that moves you
> up to having a TBR and initial SMP support.
Sorry, what's a TBR?
> But I think there are still embedded x86 clones that I am not sure
On Fri, Sep 11, 2020 at 1:07 PM Florian Weimer wrote:
> * Joel Sherrill:
>
> > With that in mind, what's the lowest/oldest i386 CPU model we
> > should consider as the new base model?
>
> The 80486 has a CMPXCHG instruction (4-byte CAS). Starting from CAS,
> you can build the rest. There might
* Joel Sherrill:
> With that in mind, what's the lowest/oldest i386 CPU model we
> should consider as the new base model?
The 80486 has a CMPXCHG instruction (4-byte CAS). Starting from CAS,
you can build the rest. There might be some caveats about the memory
model implementation (it may not be
Hi
Over at RTEMS, we ran into a case where the C++ atomics may not be right
for one of the lower level x86 models. We will investigate whether it can
be made right but this has led to the discussion of dropping older models
and setting a new minimum model. Right now, our base is a i386 w/FPU. The
On Fri, 2020-09-11 at 12:14 +0100, Richard Sandiford wrote:
> Ilya Leoshkevich writes:
> > On Fri, 2020-09-11 at 12:17 +0200, Ilya Leoshkevich wrote:
> > > On Fri, 2020-09-11 at 10:46 +0100, Richard Sandiford wrote:
> > > > Ilya Leoshkevich via Gcc writes:
> > > > > On Wed, 2020-09-09 at 16:09 -0
Hi!
On Fri, Sep 11, 2020 at 08:44:54AM +0100, Richard Sandiford wrote:
> Segher Boessenkool writes:
> > Consider cores that do not care about the "subtype" at all: when using
> > just "type", all cores have to test for "foo,foo_subtype", while with
> > a separate attribute they can just test for
On 07/09/2020 07:08, Qian, Jianhua wrote:
> Hi
>
> I'm adding a new machine model. I have a problem when writing the
> "define_insn_reservation" for instruction scheduling.
> How to write the "define_insn_reservation" for one instruction that there are
> different latencies and pipelines accordi
Ilya Leoshkevich writes:
> On Fri, 2020-09-11 at 12:17 +0200, Ilya Leoshkevich wrote:
>> On Fri, 2020-09-11 at 10:46 +0100, Richard Sandiford wrote:
>> > Ilya Leoshkevich via Gcc writes:
>> > > On Wed, 2020-09-09 at 16:09 -0500, Segher Boessenkool wrote:
>> > > > Hi Ilya,
>> > > >
>> > > > On We
On Fri, 2020-09-11 at 12:17 +0200, Ilya Leoshkevich wrote:
> On Fri, 2020-09-11 at 10:46 +0100, Richard Sandiford wrote:
> > Ilya Leoshkevich via Gcc writes:
> > > On Wed, 2020-09-09 at 16:09 -0500, Segher Boessenkool wrote:
> > > > Hi Ilya,
> > > >
> > > > On Wed, Sep 09, 2020 at 11:50:56AM +020
On Fri, 2020-09-11 at 10:46 +0100, Richard Sandiford wrote:
> Ilya Leoshkevich via Gcc writes:
> > On Wed, 2020-09-09 at 16:09 -0500, Segher Boessenkool wrote:
> > > Hi Ilya,
> > >
> > > On Wed, Sep 09, 2020 at 11:50:56AM +0200, Ilya Leoshkevich via
> > > Gcc
> > > wrote:
> > > > I have a vector
Ilya Leoshkevich via Gcc writes:
> On Wed, 2020-09-09 at 16:09 -0500, Segher Boessenkool wrote:
>> Hi Ilya,
>>
>> On Wed, Sep 09, 2020 at 11:50:56AM +0200, Ilya Leoshkevich via Gcc
>> wrote:
>> > I have a vector pseudo containing a single 128-bit value (V1TFmode)
>> > and
>> > I need to access it
Segher Boessenkool writes:
> On Thu, Sep 10, 2020 at 11:04:26AM +0100, Richard Sandiford wrote:
>> Segher Boessenkool writes:
>> > You can also use some other attributes to classify instructions, you
>> > don't have to put it all in one "type" attribute. This can of course be
>> > done later, at
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