Hi Joseph
I'll look at more detail at the other problems, but first it
seems that non-Linux GNU targets are currently broken
because many declarations that are not Linux-specific
have been added to the Linux-specific sections of
config.gcc.
Should I wait untill your patch is merged to fix this?
Gidi Nave writes:
> On Tue, Jan 11, 2011 at 7:22 PM, Ian Lance Taylor wrote:
>> Gidi Nave writes:
>>
>>> On Tue, Jan 11, 2011 at 5:34 PM, Ian Lance Taylor wrote:
>>>
So why doesn't d1 = d1 + -96 match the last instruction there?
>>> because it's: add d,d unsigned
>>> we don't have
On Tue, Jan 11, 2011 at 7:22 PM, Ian Lance Taylor wrote:
> Gidi Nave writes:
>
>> On Tue, Jan 11, 2011 at 5:34 PM, Ian Lance Taylor wrote:
>>
>>> So why doesn't d1 = d1 + -96 match the last instruction there?
>>>
>> because it's: add d,d unsigned
>> we don't have: add d,d signed
>>
>> and in
Dear Steering Committee:
The current listed maintainer for option handling is:
option handling Neil Booth n...@daikokuya.co.uk
But I'm wondering if Neil is still active. There are no replies to my
recent pings from that email address. The last recorded commit from him
in
Snapshot gcc-4.4-20110111 is now available on
ftp://gcc.gnu.org/pub/gcc/snapshots/4.4-20110111/
and on various mirrors, see http://gcc.gnu.org/mirrors.html for details.
This snapshot has been generated from the GCC 4.4 SVN branch
with the following options: svn://gcc.gnu.org/svn/gcc/branches
Gidi Nave writes:
> On Tue, Jan 11, 2011 at 5:34 PM, Ian Lance Taylor wrote:
>
>> So why doesn't d1 = d1 + -96 match the last instruction there?
>>
> because it's:add d,d unsigned
> we don't have: add d,d signed
>
> and in this case we need: d = r + (-96)
(Please don't top-post on this mai
On 01/05/2011 09:44 AM, roy rosen wrote:
2011/1/3 Jeff Law:
On 12/27/10 08:43, roy rosen wrote:
I'd recommend to try ira-improv branch. I think that part of the problem
is
in usage of cover classes. The branch removes the cover classes and
permits
IRA to use intersected register classes and t
because it's:add d,d unsigned
we don't have: add d,d signed
and in this case we need: d = r + (-96)
On Tue, Jan 11, 2011 at 5:34 PM, Ian Lance Taylor wrote:
> Gidi Nave writes:
>
>> On Tue, Jan 11, 2011 at 4:30 PM, Ian Lance Taylor wrote:
>>> Gidi Nave writes:
>>>
I have a question
On 01/03/2011 10:41 AM, Jeff Law wrote:
On 12/27/10 08:43, roy rosen wrote:
I'd recommend to try ira-improv branch. I think that part of the
problem is
in usage of cover classes. The branch removes the cover classes and
permits
IRA to use intersected register classes and that helps to assig
Gidi Nave writes:
> On Tue, Jan 11, 2011 at 4:30 PM, Ian Lance Taylor wrote:
>> Gidi Nave writes:
>>
>>> I have a question regarding Plus reload situation I ran into in my
>>> port (which was taken from branch 4.6):
>>>
>>> I got the following insn: Set d1 (plus r1 -96).
>>> d1 and r1 are 2 r
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 01/11/11 07:59, Gidi Nave wrote:
> Hi Ian,
>
> Relevant instruction supported:
>
> add r,r,r
> add r,r unsigned
> add r,r, signed
> add d,d,d
> add d,d unsigned
You're probably going to need a secondary reload to deal with this case
d = r + -const
oh,
I forgot:
move d,r(d = r)
On Tue, Jan 11, 2011 at 4:59 PM, Gidi Nave wrote:
> Hi Ian,
>
> Relevant instruction supported:
>
> add r,r,r
> add r,r unsigned
> add r,r, signed
> add d,d,d
> add d,d unsigned
>
> Thanks,
> Gal.
>
>
> On Tue, Jan 11, 2011 at 4:30 PM, Ian Lance Taylor wrote
Hi Ian,
Relevant instruction supported:
add r,r,r
add r,r unsigned
add r,r, signed
add d,d,d
add d,d unsigned
Thanks,
Gal.
On Tue, Jan 11, 2011 at 4:30 PM, Ian Lance Taylor wrote:
> Gidi Nave writes:
>
>> I have a question regarding Plus reload situation I ran into in my
>> port (which was t
Gidi Nave writes:
> I have a question regarding Plus reload situation I ran into in my
> port (which was taken from branch 4.6):
>
> I got the following insn: Set d1 (plus r1 -96).
> d1 and r1 are 2 registers from different classes.
>
> The reload (which take place at: reload1.c , gen_reload(ou
Tom de Vries writes:
> The following fix makes sure that the cached live info is invalidated:
> ...
> @@ -1865,6 +1880,7 @@ redundant_insn (rtx insn, rtx target, rt
> {
> /* Show that this insn will be used in the sequel. */
> INSN_FROM_TARGET_P (can
Hi,
I have a question regarding Plus reload situation I ran into in my
port (which was taken from branch 4.6):
I got the following insn: Set d1 (plus r1 -96).
d1 and r1 are 2 registers from different classes.
The reload (which take place at: reload1.c , gen_reload(out = d1, in =
(plus r1 -96))
On 01/10/2011 06:40 PM, Ralf Wildenhues wrote:
* Andrew Haley wrote on Fri, Jan 07, 2011 at 10:24:53AM CET:
On 01/06/2011 09:28 PM, Gerald Pfeifer wrote:
On Thu, 6 Jan 2011, Ralf Wildenhues wrote:
Does passing '-Wl,-rpath -Wl,/foo' to gcj work for a small example
program for you?
I played a
Hi all,
I would like to know if the attached patch resource-check.patch is a
good sanity check or not.
I have been working in reorg.c and running into trouble with the target
info cache in mark_target_live_regs, so I decided to write a patch that
checks consistency between cached values and recom
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