Gidi Nave <gidi.nav...@gmail.com> writes: > On Tue, Jan 11, 2011 at 4:30 PM, Ian Lance Taylor <i...@google.com> wrote: >> Gidi Nave <gidi.nav...@gmail.com> writes: >> >>> I have a question regarding Plus reload situation I ran into in my >>> port (which was taken from branch 4.6): >>> >>> I got the following insn: Set d1 (plus r1 -96). >>> d1 and r1 are 2 registers from different classes. >>> >>> The reload (which take place at: reload1.c , gen_reload(out = d1, in = >>> (plus r1 -96)) try 3 options: >>> >>> 1. switch the plus operands: >>> set d1 (plus -96 r1) >>> >>> 2. split into 2 insns - reload the const to d1 and then add r1: >>> set d1 -96 >>> set d1 (plus d1 r1) >>> >>> 3. split into 2 insns - copy r1 to d1 and then add the const: >>> set d1 r1 >>> set d1 (plus d1 -96) >>> >>> GCC tries generating the 1st option - and fails since no valid pattern is >>> found. >>> Then it tries generating the 2nd option and fails once again, since no >>> valid pattern is found. >>> Then it tries generating the 3rd option without constraint validity >>> check(emit_insn_if_valid_for_reload) like the first 2 attempts, >>> and creates a new insn which will later fail since it's not satisfying >>> it's constraints. >>> >>> My question is: why is GCC certain that one of those 3 attempts must work? >>> In my case, all 3 resulted insns are not supported by the architecture. >> >> What instructions are supported by your processor here? > > Relevant instruction supported: > > add r,r,r > add r,r unsigned > add r,r, signed > add d,d,d > add d,d unsigned
So why doesn't d1 = d1 + -96 match the last instruction there? Ian
