Update GPU node to include acd level values.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index
detected based on devicetree data.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 84 ++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 36 +++
drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 21
On 1/9/2025 1:36 PM, Krzysztof Kozlowski wrote:
> On Thu, Jan 09, 2025 at 02:10:01AM +0530, Akhil P Oommen wrote:
>> Add a new schema which extends opp-v2 to support a new vendor specific
>> property required for Adreno GPUs found in Qualcomm's SoCs. The new
>> property
On 1/9/2025 1:24 PM, neil.armstr...@linaro.org wrote:
> On 08/01/2025 21:39, Akhil P Oommen wrote:
>> When ACD feature is enabled, it triggers some internal calibrations
>> which result in a pretty long delay during the first HFI perf vote.
>> So, increase the HFI response
Adreno X1-85 has an additional bit which is at a non-contiguous
location in qfprom. Add support for this new "hi" bit along with
the speedbin mappings.
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 5 +
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 15 ++-
2 files changed, 19 inse
Update the RPMH level definitions to include TURBO_L5 corner.
Signed-off-by: Akhil P Oommen
---
include/dt-bindings/power/qcom-rpmpd.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/power/qcom-rpmpd.h
b/include/dt-bindings/power/qcom-rpmpd.h
index
anges should be picked up first.
[1] https://lore.kernel.org/lkml/20250109-gpu-acd-v4-0-08a5efaf4...@quicinc.com/
[2]
https://lore.kernel.org/linux-arm-msm/20250104-sar2130p-nvmem-v3-0-a94e0b7de...@linaro.org/
-Akhil
---
Akhil P Oommen (4):
drm/msm/adreno: Add speedbin support for X1-85
Document compatible string for the QFPROM on X1E80100 platform.
Signed-off-by: Akhil P Oommen
---
Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
b/Documentation/devicetree
Update GPU OPP table with new levels along with the speedbin
configurations.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 47 ++
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
b/arch/arm64/boot
On 1/9/2025 4:03 AM, Bjorn Andersson wrote:
> On Fri, Dec 13, 2024 at 05:01:05PM +0530, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add gpu and gmu nodes for qcs615 chipset.
>>
>
> Please resubmit this in a series together with the gpucc patch.
Sure. I
On 12/31/2024 3:09 PM, Konrad Dybcio wrote:
> On 30.12.2024 11:25 PM, Rob Herring (Arm) wrote:
>>
>> On Tue, 31 Dec 2024 02:41:05 +0530, Akhil P Oommen wrote:
>>> Add a new schema which extends opp-v2 to support a new vendor specific
>>> property required for Adr
On 12/31/2024 3:18 PM, neil.armstr...@linaro.org wrote:
> On 30/12/2024 22:11, Akhil P Oommen wrote:
>> ACD a.k.a Adaptive Clock Distribution is a feature which helps to reduce
>> the power consumption. In some chipsets, it is also a requirement to
>> support higher GPU fr
ing the same TBU.
>
> Signed-off-by: Rob Clark
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> v2: Adds a modparam to override the default behavior, for debugging
> GPU faults in cases which do not (or might not) cause lockup.
> Also, rebased to not depend on Bibek'
On 1/9/2025 7:27 PM, Konrad Dybcio wrote:
> On 8.01.2025 11:42 PM, Akhil P Oommen wrote:
>> Adreno X1-85 has an additional bit which is at a non-contiguous
>> location in qfprom. Add support for this new "hi" bit along with
>> the speedbin mappings.
>&g
Signed-off-by: Rob Clark
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> drivers/gpu/drm/msm/msm_drv.h | 11 ---
> 1 file changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index fee31680a6d5..a65
From: Jie Zhang
Add gpu and gmu nodes for qcs8300 chipset.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 93 +++
1 file changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
b/arch
From: Jie Zhang
Enable GPU for qcs8300-ride platform and provide path for zap
shader.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
b
From: Jie Zhang
Add support for Adreno 623 GPU found in QCS8300 chipsets.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8
drivers/gpu/drm/msm
From: Jie Zhang
Document Adreno 623 GMU in the dt-binding specification.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm
From: Jie Zhang
Adreno 621 has a different memory map for GPUCC block. So update
a6xx_gpu_state code to dump the correct set of gpucc registers.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 13 ++---
drivers/gpu/drm/msm
On 2/12/2025 4:26 PM, Dmitry Baryshkov wrote:
> On Wed, Feb 12, 2025 at 12:48:01PM +0530, Akhil P Oommen wrote:
>> On 2/12/2025 5:30 AM, Dmitry Baryshkov wrote:
>>> On Tue, Feb 11, 2025 at 06:41:39PM +0530, Akhil P Oommen wrote:
>>>> On 2/9/2025 9:59 PM, Dmitry Bary
On 2/12/2025 5:30 AM, Dmitry Baryshkov wrote:
> On Tue, Feb 11, 2025 at 06:41:39PM +0530, Akhil P Oommen wrote:
>> On 2/9/2025 9:59 PM, Dmitry Baryshkov wrote:
>>> On Wed, Nov 13, 2024 at 02:18:43AM +0530, Akhil P Oommen wrote:
>>>> On 10/30/2024 12:32 PM, Akhil P Oom
On 2/13/2025 10:24 PM, Dmitry Baryshkov wrote:
> On Thu, Feb 13, 2025 at 09:40:07PM +0530, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add support for Adreno 623 GPU found in QCS8300 chipsets.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P
On 2/13/2025 10:26 PM, Dmitry Baryshkov wrote:
> On Thu, Feb 13, 2025 at 09:40:09PM +0530, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add gpu and gmu nodes for qcs8300 chipset.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P Oommen
>>
On 2/13/2025 10:12 PM, Dmitry Baryshkov wrote:
> On Thu, Feb 13, 2025 at 09:40:05PM +0530, Akhil P Oommen wrote:
>
> Nit: subject needs to be fixed
That escaped my eyes. Will fix in the next rev.
-Akhil
>
>> This series adds support for A623 GPU found in QCS8300 chipsets.
-f6698603fb85
prerequisite-change-id: 20250131-b4-branch-gfx-smmu-b03261963064:v5
prerequisite-patch-id: f8fd1a2020c940e595e58a8bd3c55d00d3d87271
prerequisite-patch-id: 08a0540f75b0f95fd2018b38c9ed5c6f96433b4d
Best regards,
--
Akhil P Oommen
On 2/13/2025 10:06 PM, Konrad Dybcio wrote:
> On 13.02.2025 5:10 PM, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Adreno 621 has a different memory map for GPUCC block. So update
>> a6xx_gpu_state code to dump the correct set of gpucc registers.
>>
>> Sig
On 2/13/2025 10:51 PM, Konrad Dybcio wrote:
> On 13.02.2025 5:10 PM, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add support for Adreno 623 GPU found in QCS8300 chipsets.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P Oommen
>> ---
On 2/18/2025 11:52 PM, Rob Clark wrote:
> On Thu, Feb 13, 2025 at 8:10 AM Akhil P Oommen
> wrote:
>>
>> From: Jie Zhang
>>
>> Adreno 621 has a different memory map for GPUCC block. So update
>> a6xx_gpu_state code to dump the correct set of gpucc regis
e time),
> see https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25981.
> So let's go ahead and expose it now.
>
> Signed-off-by: Rob Clark
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> drivers/gpu/drm/msm/msm_drv.c | 1 +
> 1 file changed, 1 insertion(+)
>
>
pend. Also, calling prepare-suspend without a prior oob-gpu handshake
messes up gmu firmware's internal state. So, do that when required.
Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support")
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/m
pend. Also, calling prepare-slumber without a prior oob-gpu handshake
messes up gmu firmware's internal state. So, do that when required.
Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support")
Cc: sta...@vger.kernel.org
Signed-off-by: Akhil P Oommen
---
Changes in v2:
- Minor update
On 2/28/2025 1:59 AM, Konrad Dybcio wrote:
> On 27.02.2025 9:07 PM, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add support for Adreno 623 GPU found in QCS8300 chipsets.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P Oommen
>> ---
From: Jie Zhang
Add gpu and gmu nodes for qcs8300 chipset.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 93 +++
1 file changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
b/arch
From: Jie Zhang
Add support for Adreno 623 GPU found in QCS8300 chipsets.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8
drivers/gpu/drm/msm
From: Jie Zhang
Enable GPU for qcs8300-ride platform and provide path for zap
shader.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
Reviewed-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64
From: Jie Zhang
Some GPUs have different memory map for GPUCC block. So split out the
gpucc range from a6xx_gmu_cx_registers to a separate block to
accommodate those GPUs.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 8
From: Jie Zhang
Document Adreno 623 GMU in the dt-binding specification.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
Reviewed-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation
-branch-gfx-smmu-b03261963064:v5
prerequisite-patch-id: f8fd1a2020c940e595e58a8bd3c55d00d3d87271
prerequisite-patch-id: 08a0540f75b0f95fd2018b38c9ed5c6f96433b4d
Best regards,
--
Akhil P Oommen
From: Jie Zhang
Adreno 621 has a different memory map for GPUCC block. So update
a6xx_gpu_state code to dump the correct set of gpucc registers.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 9 +++--
drivers/gpu/drm/msm/adreno
On 2/28/2025 4:56 AM, Dmitry Baryshkov wrote:
> On Fri, Feb 28, 2025 at 01:37:51AM +0530, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add support for Adreno 623 GPU found in QCS8300 chipsets.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P
On 2/28/2025 7:53 PM, Rob Herring (Arm) wrote:
>
> On Fri, 28 Feb 2025 01:37:48 +0530, Akhil P Oommen wrote:
>> This series adds support for A623 GPU found in QCS8300 chipsets. This
>> GPU IP is very similar to A621 GPU, except for the UBWC configuration
>> and the GMU
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