From: Jie Zhang <quic_ji...@quicinc.com>
Add gpu and gmu nodes for qcs8300 chipset.
Signed-off-by: Jie Zhang <quic_ji...@quicinc.com>
Signed-off-by: Akhil P Oommen <quic_akhi...@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 93 +++++++++++++++++++++++++++++++++++
1 file changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index f1c90db7b0e6..2dc487dcc584 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -2660,6 +2660,99 @@ serdes0: phy@8909000 {
status = "disabled";
};
+ gpu: gpu@3d00000 {
+ compatible = "qcom,adreno-623.0", "qcom,adreno";
+ reg = <0x0 0x03d00000 0x0 0x40000>,
+ <0x0 0x03d9e000 0x0 0x1000>,
+ <0x0 0x03d61000 0x0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&adreno_smmu 0 0xc00>,
+ <&adreno_smmu 1 0xc00>;
+ operating-points-v2 = <&gpu_opp_table>;
+ qcom,gmu = <&gmu>;
+ interconnects = <&gem_noc MASTER_GFX3D
QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1
QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "gfx-mem";
+ #cooling-cells = <2>;
+
+ status = "disabled";
+
+ gpu_zap_shader: zap-shader {
+ memory-region = <&gpu_microcode_mem>;
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-877000000 {
+ opp-hz = /bits/ 64 <877000000>;
+ opp-level =
<RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ opp-peak-kBps = <12484375>;
+ };
+
+ opp-780000000 {
+ opp-hz = /bits/ 64 <780000000>;
+ opp-level =
<RPMH_REGULATOR_LEVEL_TURBO>;
+ opp-peak-kBps = <10687500>;
+ };
+
+ opp-599000000 {
+ opp-hz = /bits/ 64 <599000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-peak-kBps = <8171875>;
+ };
+
+ opp-479000000 {
+ opp-hz = /bits/ 64 <479000000>;
+ opp-level =
<RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <5285156>;
+ };
+ };
+ };
+
+ gmu: gmu@3d6a000 {
+ compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu";
+ reg = <0x0 0x03d6a000 0x0 0x34000>,
+ <0x0 0x03de0000 0x0 0x10000>,
+ <0x0 0x0b290000 0x0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc";
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "ahb",
+ "hub",
+ "smmu_vote";
+ power-domains = <&gpucc GPU_CC_CX_GDSC>,
+ <&gpucc GPU_CC_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+ iommus = <&adreno_smmu 5 0xc00>;
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level =
<RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
gpucc: clock-controller@3d90000 {
compatible = "qcom,qcs8300-gpucc";
reg = <0x0 0x03d90000 0x0 0xa000>;
--
2.45.2
