From: Puranam V G Tejaswi
Add gpu and gmu nodes for sa8775p based platforms.
Signed-off-by: Puranam V G Tejaswi
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 8
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 75 ++
2 files
On 11/7/2024 2:25 PM, neil.armstr...@linaro.org wrote:
> On 06/11/2024 02:44, Akhil P Oommen wrote:
>> On 11/4/2024 9:14 PM, neil.armstr...@linaro.org wrote:
>>> On 11/10/2024 22:29, Akhil P Oommen wrote:
>>>> ACD a.k.a Adaptive Clock Distribution is a feature which
On Mon, Oct 14, 2024 at 09:40:13AM +0200, Krzysztof Kozlowski wrote:
> On Sat, Oct 12, 2024 at 01:59:30AM +0530, Akhil P Oommen wrote:
> > Update GPU node to include acd level values.
> >
> > Signed-off-by: Akhil P Oommen
> > ---
> > arch/arm64
On 11/7/2024 8:01 PM, neil.armstr...@linaro.org wrote:
> On 07/11/2024 13:46, Akhil P Oommen wrote:
>> On 11/7/2024 2:25 PM, neil.armstr...@linaro.org wrote:
>>> On 06/11/2024 02:44, Akhil P Oommen wrote:
>>>> On 11/4/2024 9:14 PM, neil.armstr...@linaro.org wrote:
&g
On 11/25/2024 1:44 PM, Neil Armstrong wrote:
> On 23/11/2024 23:59, Akhil P Oommen wrote:
>> On Tue, Nov 19, 2024 at 06:56:43PM +0100, Neil Armstrong wrote:
>>> When requesting a DDR bandwidth level along a GPU frequency
>>> level via the GMU, we can also specify t
On 11/25/2024 1:42 PM, Neil Armstrong wrote:
> On 23/11/2024 23:46, Akhil P Oommen wrote:
>> On Sun, Nov 24, 2024 at 02:52:46AM +0530, Akhil P Oommen wrote:
>>> On Tue, Nov 19, 2024 at 06:56:40PM +0100, Neil Armstrong wrote:
>>>> The Adreno GMU Management Unit (GMU
On 11/25/2024 1:46 PM, Neil Armstrong wrote:
> On 23/11/2024 20:43, Akhil P Oommen wrote:
>> On Tue, Nov 19, 2024 at 06:56:39PM +0100, Neil Armstrong wrote:
>>> The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth
>>> along the Frequency and Power Doma
On 11/14/2024 8:57 PM, Konrad Dybcio wrote:
> On 12.11.2024 10:15 PM, Akhil P Oommen wrote:
>> On 11/11/2024 8:38 PM, Rob Clark wrote:
>>> On Sun, Nov 10, 2024 at 9:31 AM Bjorn Andersson
>>> wrote:
>>>>
>>>> Support for per-process page tables re
On 11/1/2024 9:54 PM, Akhil P Oommen wrote:
> On 10/25/2024 11:58 AM, Dmitry Baryshkov wrote:
>> On Thu, Oct 24, 2024 at 12:56:58AM +0530, Akhil P Oommen wrote:
>>> On 10/22/2024 11:19 AM, Krzysztof Kozlowski wrote:
>>>> On Mon, Oct 21, 2024 at 05:23:43PM +0530, Akh
On 11/15/2024 3:54 AM, Dmitry Baryshkov wrote:
> Hello Akhil,
>
> On Thu, 14 Nov 2024 at 20:50, Akhil P Oommen wrote:
>>
>> On 11/1/2024 9:54 PM, Akhil P Oommen wrote:
>>> On 10/25/2024 11:58 AM, Dmitry Baryshkov wrote:
>>>> On Thu, Oct 24, 2024
On Tue, Nov 19, 2024 at 06:56:40PM +0100, Neil Armstrong wrote:
> The Adreno GMU Management Unit (GMU) can also scale DDR Bandwidth along
> the Frequency and Power Domain level, but by default we leave the
> OPP core scale the interconnect ddr path.
>
> In order to calculate vote values used by th
On Sun, Nov 24, 2024 at 02:52:46AM +0530, Akhil P Oommen wrote:
> On Tue, Nov 19, 2024 at 06:56:40PM +0100, Neil Armstrong wrote:
> > The Adreno GMU Management Unit (GMU) can also scale DDR Bandwidth along
> > the Frequency and Power Domain level, but by default we leave the
> &g
On Tue, Nov 19, 2024 at 06:56:43PM +0100, Neil Armstrong wrote:
> When requesting a DDR bandwidth level along a GPU frequency
> level via the GMU, we can also specify the bus bandwidth usage in a 16bit
> quantitized value.
>
> For now simply request the maximum bus usage.
Why? You don't care abou
On 11/26/2024 7:42 PM, Krzysztof Kozlowski wrote:
> On 26/11/2024 15:06, Akhil P Oommen wrote:
>> A612 GPU requires an additional smmu_vote clock. Update the bindings to
>> reflect this.
>>
>> Signed-off-by: Akhil P Oommen
>> ---
>> .../devicetree/b
On 11/26/2024 7:36 PM, Akhil P Oommen wrote:
> A612 GPU requires an additional smmu_vote clock. Update the bindings to
> reflect this.
>
> Signed-off-by: Akhil P Oommen
> ---
> .../devicetree/bindings/display/msm/gpu.yaml | 28
> --
> 1 fil
From: Jie Zhang
Add gpu and gmu nodes for qcs615 chipset.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs615.dtsi | 86
1 file changed, 86 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi
b/arch
From: Jie Zhang
Enable GPU for qcs615-ride platform and provide path for zap
shader.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
b
This series adds support for Adreno 612 to QCS615 chipset's devicetree.
DRM driver's support was posted earlier and can be found here:
https://patchwork.freedesktop.org/patch/626066/
Patch#1 is for Rob Clark and the other 2 for Bjorn
Signed-off-by: Akhil P Oommen
---
Akhil P
A612 GPU requires an additional smmu_vote clock. Update the bindings to
reflect this.
Signed-off-by: Akhil P Oommen
---
.../devicetree/bindings/display/msm/gpu.yaml | 28 --
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree
On 11/25/2024 10:16 PM, Dmitry Baryshkov wrote:
> On Mon, Nov 25, 2024 at 10:03:00PM +0530, Akhil P Oommen wrote:
>> There are a few chipsets which don't have system cache a.k.a LLC.
>> Currently, the assumption in the driver is that the system cache
>> availability corre
with enabling RGMU at the moment, RGMU is
entirely skipped in this patch.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
Reviewed-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 15 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
to v1:
https://lore.kernel.org/r/20241101-a612-gpu-support-v1-1-bdfe8f6d9...@quicinc.com
---
Akhil P Oommen (1):
drm/msm/adreno: Introduce ADRENO_QUIRK_NO_SYSCACHE
Jie Zhang (1):
drm/msm/a6xx: Add support for Adreno 612
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 18 -
driver
esnot have a system cache. So,
introduce an Adreno Quirk flag to check support for system cache
instead of using gmu_wrapper flag.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 3 ++-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 +--
drivers/gpu/drm/msm/a
On 11/28/2024 3:55 PM, Neil Armstrong wrote:
> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along
> the Frequency and Power Domain level, but by default we leave the
> OPP core scale the interconnect ddr path.
>
> While scaling via the interconnect path was sufficient, newer G
On 11/29/2024 9:03 PM, Konrad Dybcio wrote:
> On 28.11.2024 11:25 AM, Neil Armstrong wrote:
>> The Adreno GPU Management Unit (GMU) can also scale the DDR Bandwidth
>> along the Frequency and Power Domain level, until now we left the OPP
>> core scale the OPP bandwidth via the interconnect path.
>>
On 11/27/2024 9:17 PM, neil.armstr...@linaro.org wrote:
> On 27/11/2024 16:29, Akhil P Oommen wrote:
>> On 11/25/2024 1:42 PM, Neil Armstrong wrote:
>>> On 23/11/2024 23:46, Akhil P Oommen wrote:
>>>> On Sun, Nov 24, 2024 at 02:52:46AM +0530, Akhil P Oommen wrote:
&g
On 11/28/2024 3:55 PM, Neil Armstrong wrote:
> Even if the code uses ARRAY_SIZE() to fill those tables,
> it's still a best practice to not use magic values for
> tables in structs.
>
> Suggested-by: Dmitry Baryshkov
> Signed-off-by: Neil Armstrong
Reviewed-by:
On 11/30/2024 7:01 PM, Konrad Dybcio wrote:
> On 25.11.2024 5:33 PM, Akhil P Oommen wrote:
>> There are a few chipsets which don't have system cache a.k.a LLC.
>> Currently, the assumption in the driver is that the system cache
>> availability correlates with the pres
On 12/5/2024 3:20 AM, Rob Clark wrote:
> On Wed, Dec 4, 2024 at 1:47 PM Rob Clark wrote:
>>
>> On Wed, Dec 4, 2024 at 11:04 AM Akhil P Oommen
>> wrote:
>>>
>>> On 12/1/2024 10:06 PM, Rob Clark wrote:
>>>> On Sat, Nov 30, 2024 at 12:30 PM Akhi
On 12/1/2024 10:06 PM, Rob Clark wrote:
> On Sat, Nov 30, 2024 at 12:30 PM Akhil P Oommen
> wrote:
>>
>> On 11/30/2024 7:01 PM, Konrad Dybcio wrote:
>>> On 25.11.2024 5:33 PM, Akhil P Oommen wrote:
>>>> There are a few chipsets which don't have
On 12/4/2024 9:05 PM, Neil Armstrong wrote:
> On 02/12/2024 09:46, Neil Armstrong wrote:
>> On 30/11/2024 22:49, Akhil P Oommen wrote:
>>> On 11/28/2024 3:55 PM, Neil Armstrong wrote:
>>>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along
>&
On 12/5/2024 8:31 PM, Neil Armstrong wrote:
> The Adreno GPU Management Unit (GMU) can also scale the ddr
> bandwidth along the frequency and power domain level, but for
> now we statically fill the bw_table with values from the
> downstream driver.
>
> Only the first entry is used, which is a dis
gt; Since we now vote for all resources via the GMU, setting the OPP
> is no more needed, so we can completely skip calling
> dev_pm_opp_set_opp() in this situation.
>
> Reviewed-by: Dmitry Baryshkov
> Signed-off-by: Neil Armstrong
Reviewed-by: Akhil P O
by: Neil Armstrong
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 22 ++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> b/drivers/gpu/d
On 12/5/2024 8:31 PM, Neil Armstrong wrote:
> Each GPU OPP requires a specific peak DDR bandwidth, let's add
> those to each OPP and also the related interconnect path.
>
> Signed-off-by: Neil Armstrong
I haven't checked each bw value, still
Reviewed-by: Akhil P Oommen
On 12/9/2024 6:32 PM, Akhil P Oommen wrote:
> On 12/5/2024 8:31 PM, Neil Armstrong wrote:
>> Each GPU OPP requires a specific peak DDR bandwidth, let's add
>> those to each OPP and also the related interconnect path.
>>
>> Signed-off-by: Neil Armstrong
>
>
figuration, this patch doesn't have any impact.
Driver loads secure firmware based on other existing hints.
Signed-off-by: Akhil P Oommen
---
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 82 +++
1 file changed, 54 insertions(+), 28 deletions(-)
diff --git a/driv
dth.
> The AB vote will be calculated later when setting the frequency.
>
> The vote array will then be used to dynamically generate the GMU
> bw_table sent during the GMU power-up.
>
> Signed-off-by: Neil Armstrong
Reviewed-by: Akhil P Oo
On 12/10/2024 1:24 AM, Rob Clark wrote:
> On Mon, Dec 9, 2024 at 12:20 AM Akhil P Oommen
> wrote:
>>
>> When kernel is booted in EL2, SECVID registers are accessible to the
>> KMD. So we can use that to switch GPU's secure mode to avoid dependency
>> on Zap fir
On 12/9/2024 8:33 PM, Konrad Dybcio wrote:
> On 9.12.2024 9:19 AM, Akhil P Oommen wrote:
>> When kernel is booted in EL2, SECVID registers are accessible to the
>> KMD. So we can use that to switch GPU's secure mode to avoid dependency
>> on Zap firmware. Also, we ca
corruption, there's some lines(mostly white)
> > on my yoga slim 7x that appear on the bottom of the screen. When I
> > move my cursor in swaywm over it, the lines get occluded by the cursor
> > and screenshots don't show these lines.
> >
> > Best Reg
On 1/3/2025 1:00 AM, Akhil P Oommen wrote:
> On 1/3/2025 12:02 AM, Rob Clark wrote:
>> From: Rob Clark
>>
>> On mmu-500, stall-on-fault seems to stall all context banks, causing the
>> GMU to misbehave. So limit this feature to smmu-v2 for now.
>>
>> Thi
On 12/31/2024 4:02 PM, Konrad Dybcio wrote:
> On 30.12.2024 10:11 PM, Akhil P Oommen wrote:
>> Add a module param to disable ACD which will help to quickly rule it
>> out for any GPU issues.
>>
>> Signed-off-by: Akhil P Oommen
>> ---
>
> Is that something
Fix the following for qmp_get() errors:
1. Correctly handle probe defer for A6x GPUs
2. Ignore other errors because those are okay when GPU ACD is
not required. They are checked again during gpu acd probe.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 5 +++--
1
ng for opp-table (Krzysztof)
- Link to v1:
https://lore.kernel.org/r/20241012-gpu-acd-v1-0-1e5e91aa9...@quicinc.com
---
Akhil P Oommen (6):
drm/msm/adreno: Add support for ACD
drm/msm: a6x: Rework qmp_get() error handling
drm/msm/adreno: Add module param to disable ACD
d
detected based on devicetree data.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 84 ++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 36 +++
drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 21
Add a module param to disable ACD which will help to quickly rule it
out for any GPU issues.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 +++
drivers/gpu/drm/msm/adreno/adreno_device.c | 4
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu
AINTAINERS file include the new opp-v2-qcom-adreno.yaml.
Cc: Rob Clark
Signed-off-by: Akhil P Oommen
---
.../bindings/opp/opp-v2-qcom-adreno.yaml | 97 ++
MAINTAINERS| 1 +
2 files changed, 98 insertions(+)
diff --git a/Documenta
Update GPU node to include acd level values.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index
Now that we have ACD support for GPU, add additional OPPs up to
Turbo L3 which are supported across all existing SKUs.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100
On 2/9/2025 9:59 PM, Dmitry Baryshkov wrote:
> On Wed, Nov 13, 2024 at 02:18:43AM +0530, Akhil P Oommen wrote:
>> On 10/30/2024 12:32 PM, Akhil P Oommen wrote:
>>> From: Puranam V G Tejaswi
>>>
>>> Enable GPU for sa8775p-ride platform and provide path for z
On 12/6/2024 1:16 AM, Konrad Dybcio wrote:
> On 26.11.2024 3:06 PM, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add gpu and gmu nodes for qcs615 chipset.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P Oommen
>> ---
On 12/11/2024 6:43 AM, Bjorn Andersson wrote:
> On Tue, Dec 10, 2024 at 02:22:27AM +0530, Akhil P Oommen wrote:
>> On 12/10/2024 1:24 AM, Rob Clark wrote:
>>> On Mon, Dec 9, 2024 at 12:20 AM Akhil P Oommen
>>> wrote:
>>>>
>>>> When kernel is bo
On 12/11/2024 2:24 AM, Elliot Berman wrote:
> On Mon, Dec 09, 2024 at 01:49:15PM +0530, Akhil P Oommen wrote:
>> When kernel is booted in EL2, SECVID registers are accessible to the
>> KMD. So we can use that to switch GPU's secure mode to avoid dependency
>> on Zap firmw
On 12/10/2024 3:26 AM, Rob Clark wrote:
> On Mon, Dec 9, 2024 at 12:52 PM Akhil P Oommen
> wrote:
>>
>> On 12/10/2024 1:24 AM, Rob Clark wrote:
>>> On Mon, Dec 9, 2024 at 12:20 AM Akhil P Oommen
>>> wrote:
>>>>
>>>> When kernel is bo
On 12/5/2024 10:24 PM, Rob Clark wrote:
> From: Rob Clark
>
> Performance counter usage falls into two categories:
>
> 1. Local usage, where the counter configuration, start, and end read
>happen within (locally to) a single SUBMIT. In this case, there is
>no dependency on counter confi
On 12/13/2024 11:20 PM, Rob Clark wrote:
> On Fri, Dec 13, 2024 at 8:47 AM Akhil P Oommen
> wrote:
>>
>> On 12/12/2024 10:42 PM, Rob Clark wrote:
>>> On Thu, Dec 12, 2024 at 9:08 AM Rob Clark wrote:
>>>>
>>>> On Thu, Dec 12, 2024 at 7:59 AM Ak
On 12/16/2024 10:28 PM, Connor Abbott wrote:
> On Mon, Dec 16, 2024 at 11:55 AM Akhil P Oommen
> wrote:
>>
>> On 12/13/2024 10:40 PM, Antonino Maniscalco wrote:
>>> On 12/13/24 5:50 PM, Akhil P Oommen wrote:
>>>> On 12/12/2024 9:44 PM, Antonino Maniscalco wr
On 12/16/2024 10:40 PM, Rob Clark wrote:
> From: Rob Clark
>
> On mmu-500, stall-on-fault seems to stall all context banks, causing the
> GMU to misbehave. So limit this feature to smmu-v2 for now.
>
> This fixes an issue with an older mesa bug taking outo the system
> because of GMU going off
On 12/16/2024 3:13 PM, neil.armstr...@linaro.org wrote:
> On 14/12/2024 00:46, Konrad Dybcio wrote:
>> On 13.12.2024 5:55 PM, Akhil P Oommen wrote:
>>> On 12/13/2024 10:10 PM, neil.armstr...@linaro.org wrote:
>>>> On 13/12/2024 17:31, Konrad Dybcio wrote:
>>&g
On 12/13/2024 10:40 PM, Antonino Maniscalco wrote:
> On 12/13/24 5:50 PM, Akhil P Oommen wrote:
>> On 12/12/2024 9:44 PM, Antonino Maniscalco wrote:
>>> On 12/12/24 4:58 PM, Akhil P Oommen wrote:
>>>> On 12/5/2024 10:24 PM, Rob Clark wrote:
>>>>> Fro
propriate bandwidth level while voting for a gpu frequency.
>
> Signed-off-by: Neil Armstrong
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 48
> ++-
> 1 file changed, 47 insertions(+), 1 deletion(-)
>
On 12/17/2024 2:21 AM, Rob Clark wrote:
> On Mon, Dec 16, 2024 at 12:25 PM Akhil P Oommen
> wrote:
>>
>> On 12/16/2024 10:28 PM, Connor Abbott wrote:
>>> On Mon, Dec 16, 2024 at 11:55 AM Akhil P Oommen
>>> wrote:
>>>>
>>>> On 12/13/2024
with enabling RGMU at the moment, RGMU is
entirely skipped in this patch.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
Reviewed-by: Konrad Dybcio
---
Mesa support is already available for A612. Verified Glmark2 with
weston.
Some dependencies for the devicetree change are not yet avai
On 12/13/2024 4:05 PM, Akhil P Oommen wrote:
> This series adds support for Adreno 612 to QCS615 chipset's devicetree.
> DRM driver's support was posted earlier and can be found here:
> https://patchwork.freedesktop.org/patch/626066/
>
> Patch#1 & #2 are for
From: Lijuan Gao
Add a compatible for the Power Domain Controller on QCS615 platform.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Lijuan Gao
---
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetr
This series adds support for Adreno 612 to QCS615 chipset's devicetree.
DRM driver's support was posted earlier and can be found here:
https://patchwork.freedesktop.org/patch/626066/
Patch#1 & #2 are for Rob Clark and the other 2 for Bjorn
Signed-off-by: Akhil P Oommen
---
esn't require iommu & opp table.
Signed-off-by: Akhil P Oommen
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
b/Documentation/devicetree/bindin
A612 GPU requires an additional smmu_vote clock. Update the bindings to
reflect this.
Signed-off-by: Akhil P Oommen
---
.../devicetree/bindings/display/msm/gpu.yaml | 36 ++
1 file changed, 36 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm
From: Jie Zhang
Add gpu and gmu nodes for qcs615 chipset.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
Reviewed-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qcs615.dtsi | 88
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot
From: Jie Zhang
Enable GPU for qcs615-ride platform and provide path for zap
shader.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
b
This series adds support for Adreno 612 to QCS615 chipset's devicetree.
DRM driver's support was posted earlier and can be found here:
https://patchwork.freedesktop.org/patch/626066/
Patch#1 & #2 are for Rob Clark and the other 2 for Bjorn
Signed-off-by: Akhil P Oommen
---
On 12/13/2024 4:54 PM, Akhil P Oommen wrote:
> From: Lijuan Gao
>
> Add a compatible for the Power Domain Controller on QCS615 platform.
>
> Reviewed-by: Krzysztof Kozlowski
> Signed-off-by: Lijuan Gao
> ---
> Documentation/devicetree/bindings/interrupt-controller/
On 12/13/2024 4:54 PM, Akhil P Oommen wrote:
> This series adds support for Adreno 612 to QCS615 chipset's devicetree.
> DRM driver's support was posted earlier and can be found here:
> https://patchwork.freedesktop.org/patch/626066/
>
> Patch#1 & #2 are for
This series adds support for Adreno 612 to QCS615 chipset's devicetree.
DRM driver's support was posted earlier and can be found here:
https://patchwork.freedesktop.org/patch/626066/
Patch#1 & #2 are for Rob Clark and the other 2 for Bjorn
Signed-off-by: Akhil P Oommen
---
A612 GPU requires an additional smmu_vote clock. Update the bindings to
reflect this.
Signed-off-by: Akhil P Oommen
---
.../devicetree/bindings/display/msm/gpu.yaml | 36 ++
1 file changed, 36 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm
esn't require iommu & opp table.
Signed-off-by: Akhil P Oommen
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
b/Documentation/devicetree/bindin
From: Jie Zhang
Add gpu and gmu nodes for qcs615 chipset.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
Reviewed-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qcs615.dtsi | 88
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot
From: Jie Zhang
Enable GPU for qcs615-ride platform and provide path for zap
shader.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
b
On 12/12/2024 10:42 PM, Rob Clark wrote:
> On Thu, Dec 12, 2024 at 9:08 AM Rob Clark wrote:
>>
>> On Thu, Dec 12, 2024 at 7:59 AM Akhil P Oommen
>> wrote:
>>>
>>> On 12/5/2024 10:24 PM, Rob Clark wrote:
>>>> From: Rob Clark
>>&g
On 12/12/2024 9:44 PM, Antonino Maniscalco wrote:
> On 12/12/24 4:58 PM, Akhil P Oommen wrote:
>> On 12/5/2024 10:24 PM, Rob Clark wrote:
>>> From: Rob Clark
>>>
>>> Performance counter usage falls into two categories:
>>>
>>> 1. Local usage
On 12/13/2024 10:10 PM, neil.armstr...@linaro.org wrote:
> On 13/12/2024 17:31, Konrad Dybcio wrote:
>> On 13.12.2024 5:28 PM, neil.armstr...@linaro.org wrote:
>>> On 13/12/2024 16:37, Konrad Dybcio wrote:
>>>> On 13.12.2024 2:12 PM, Akhil P Oommen wrote:
>
;>>> is in place, declare the Bus Control Modules (BCMs) and the
>>>> corresponding parameters in the GPU info struct.
>>>>
>>>> Reviewed-by: Dmitry Baryshkov
>>>> Reviewed-by: Akhil P Oommen
>>>> Signed-off-by: Neil Armstrong
>&
On 12/13/2024 4:27 PM, Konrad Dybcio wrote:
> On 13.12.2024 11:35 AM, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add gpu and gmu nodes for qcs615 chipset.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P Oommen
>> Reviewed-by: Dmitry B
On 12/13/2024 4:23 PM, Konrad Dybcio wrote:
> On 13.12.2024 11:35 AM, Akhil P Oommen wrote:
>> RGMU a.k.a Reduced Graphics Management Unit is a small state machine
>> with the sole purpose of providing IFPC support. Compared to GMU, it
>> doesn't manage GPU clock, voltage
he AB is calculated with a default 25% of the bandwidth like the
>>> downstream implementation too inform the GMU firmware the minimal
>>> quantity of bandwidth we require for this OPP.
>>>
>>> Since we now vote for all resources via the GMU, setting the OPP
&g
On Tue, Nov 19, 2024 at 06:56:37PM +0100, Neil Armstrong wrote:
> Half of the current "Quirks" are in fact features, so rename
> the defines with FEAT instead of QUIRK.
>
> They will be moved in a separate bitfield in a second time.
>
> No functional changes.
>
> Signed-off-by: Neil Armstrong
>
On Tue, Nov 19, 2024 at 06:56:39PM +0100, Neil Armstrong wrote:
> The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth
> along the Frequency and Power Domain level, but by default we leave the
> OPP core vote for the interconnect ddr path.
>
> While scaling via the interconnect pa
On 1/17/2025 2:46 AM, Konrad Dybcio wrote:
> On 15.01.2025 8:59 PM, Dmitry Baryshkov wrote:
>> On Thu, Jan 16, 2025 at 01:07:17AM +0530, Akhil P Oommen wrote:
>>> On 1/9/2025 7:27 PM, Konrad Dybcio wrote:
>>>> On 8.01.2025 11:42 PM, Akhil P Oommen wrote:
>>&g
On 1/10/2025 4:37 AM, Rob Clark wrote:
> From: Rob Clark
>
> If userspace is trying to achieve a timeout of zero, let 'em have it.
> Only round up if the timeout is greater than zero.
>
> Fixes: 4969bccd5f4e ("drm/msm: Avoid rounding down to zero jiffies")
> Signed-off-by: Rob Clark
> ---
> dr
ybcio
For the whole series:
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> Konrad Dybcio (2):
> drm/msm: registers: Add GMU FW version register
> drm/msm/a6xx: Print GMU core firmware version at boot
>
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 +++
goto out;
> }
>
> @@ -513,12 +504,12 @@ static struct drm_syncobj **msm_parse_deps(struct
> msm_gem_submit *submit,
>
> if (syncobj_desc.point &&
> !drm_core_check_feature(submit->dev,
> DRIVER_SYNCOBJ_TIMELINE)) {
> - ret = -EOPNOTSUPP;
> + ret = SUBMIT_ERROR(EOPNOTSUPP, submit, "syncobj
> timeline unsupported");
> break;
> }
>
> if (syncobj_desc.flags & ~MSM_SUBMIT_SYNCOBJ_FLAGS) {
> - ret = -EINVAL;
> + ret = -SUBMIT_ERROR(EINVAL, submit, "invalid syncobj
> flags");
> break;
> }
>
> @@ -531,7 +522,7 @@ static struct drm_syncobj **msm_parse_deps(struct
> msm_gem_submit *submit,
> syncobjs[i] =
> drm_syncobj_find(file, syncobj_desc.handle);
> if (!syncobjs[i]) {
> - ret = -EINVAL;
> + ret = SUBMIT_ERROR(EINVAL, submit, "invalid
> syncobj handle");
Just to be more useful, probably we can print the index or the handle
here. Anyway
Reviewed-by: Akhil P Oommen
-Akhil.
On 12/21/2024 2:28 AM, Dmitry Baryshkov wrote:
> On Fri, Dec 20, 2024 at 08:56:31PM +0100, Konrad Dybcio wrote:
>> On 13.12.2024 12:46 PM, Akhil P Oommen wrote:
>>> From: Jie Zhang
>>>
>>> Add support for Adreno 612 GPU found in SM6150/QCS615 chipsets.
>>
On 12/23/2024 5:24 PM, Dmitry Baryshkov wrote:
> On Mon, Dec 23, 2024 at 12:31:27PM +0100, Konrad Dybcio wrote:
>> On 4.12.2024 7:18 PM, Akhil P Oommen wrote:
>>> On 11/16/2024 1:17 AM, Dmitry Baryshkov wrote:
>>>> On Fri, 15 Nov 2024 at 19:54, Akhil P Oommen
&g
Now that we have ACD support for GPU, add additional OPPs up to
Turbo L3 which are supported across all existing SKUs.
Reviewed-by: Konrad Dybcio
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 16 +++-
1 file changed, 15 insertions(+), 1 deletion
AINTAINERS file include the new opp-v2-qcom-adreno.yaml.
Cc: Rob Clark
Signed-off-by: Akhil P Oommen
---
.../bindings/opp/opp-v2-qcom-adreno.yaml | 97 ++
MAINTAINERS| 1 +
2 files changed, 98 insertions(+)
diff --git a/Documenta
Fix the following for qmp_get() errors:
1. Correctly handle probe defer for A6x GPUs
2. Ignore other errors because those are okay when GPU ACD is
not required. They are checked again during gpu acd probe.
Reviewed-by: Konrad Dybcio
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno
ink to v1:
https://lore.kernel.org/r/20241012-gpu-acd-v1-0-1e5e91aa9...@quicinc.com
---
Akhil P Oommen (7):
drm/msm/adreno: Add support for ACD
drm/msm/a6xx: Increase HFI response timeout
drm/msm: a6x: Rework qmp_get() error handling
drm/msm/adreno: Add module param to disa
Add a module param to disable ACD which will help to quickly rule it
out for any GPU issues.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 +++
drivers/gpu/drm/msm/adreno/adreno_device.c | 4
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu
When ACD feature is enabled, it triggers some internal calibrations
which result in a pretty long delay during the first HFI perf vote.
So, increase the HFI response timeout to match the downstream driver.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 4 ++--
1 file
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