Update GPU node to include acd level values.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index
detected based on devicetree data.
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 84 ++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 36 +++
drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 21
On 1/9/2025 1:36 PM, Krzysztof Kozlowski wrote:
> On Thu, Jan 09, 2025 at 02:10:01AM +0530, Akhil P Oommen wrote:
>> Add a new schema which extends opp-v2 to support a new vendor specific
>> property required for Adreno GPUs found in Qualcomm's SoCs. The new
>> property
On 1/9/2025 1:24 PM, neil.armstr...@linaro.org wrote:
> On 08/01/2025 21:39, Akhil P Oommen wrote:
>> When ACD feature is enabled, it triggers some internal calibrations
>> which result in a pretty long delay during the first HFI perf vote.
>> So, increase the HFI response
Adreno X1-85 has an additional bit which is at a non-contiguous
location in qfprom. Add support for this new "hi" bit along with
the speedbin mappings.
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 5 +
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 15 ++-
2 files changed, 19 inse
Update the RPMH level definitions to include TURBO_L5 corner.
Signed-off-by: Akhil P Oommen
---
include/dt-bindings/power/qcom-rpmpd.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/power/qcom-rpmpd.h
b/include/dt-bindings/power/qcom-rpmpd.h
index
anges should be picked up first.
[1] https://lore.kernel.org/lkml/20250109-gpu-acd-v4-0-08a5efaf4...@quicinc.com/
[2]
https://lore.kernel.org/linux-arm-msm/20250104-sar2130p-nvmem-v3-0-a94e0b7de...@linaro.org/
-Akhil
---
Akhil P Oommen (4):
drm/msm/adreno: Add speedbin support for X1-85
Document compatible string for the QFPROM on X1E80100 platform.
Signed-off-by: Akhil P Oommen
---
Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
b/Documentation/devicetree
Update GPU OPP table with new levels along with the speedbin
configurations.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 47 ++
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
b/arch/arm64/boot
On 1/9/2025 4:03 AM, Bjorn Andersson wrote:
> On Fri, Dec 13, 2024 at 05:01:05PM +0530, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add gpu and gmu nodes for qcs615 chipset.
>>
>
> Please resubmit this in a series together with the gpucc patch.
Sure. I
On 12/31/2024 3:09 PM, Konrad Dybcio wrote:
> On 30.12.2024 11:25 PM, Rob Herring (Arm) wrote:
>>
>> On Tue, 31 Dec 2024 02:41:05 +0530, Akhil P Oommen wrote:
>>> Add a new schema which extends opp-v2 to support a new vendor specific
>>> property required for Adr
On 12/31/2024 3:18 PM, neil.armstr...@linaro.org wrote:
> On 30/12/2024 22:11, Akhil P Oommen wrote:
>> ACD a.k.a Adaptive Clock Distribution is a feature which helps to reduce
>> the power consumption. In some chipsets, it is also a requirement to
>> support higher GPU fr
ing the same TBU.
>
> Signed-off-by: Rob Clark
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> v2: Adds a modparam to override the default behavior, for debugging
> GPU faults in cases which do not (or might not) cause lockup.
> Also, rebased to not depend on Bibek'
On 1/9/2025 7:27 PM, Konrad Dybcio wrote:
> On 8.01.2025 11:42 PM, Akhil P Oommen wrote:
>> Adreno X1-85 has an additional bit which is at a non-contiguous
>> location in qfprom. Add support for this new "hi" bit along with
>> the speedbin mappings.
>&g
Signed-off-by: Rob Clark
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> drivers/gpu/drm/msm/msm_drv.h | 11 ---
> 1 file changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index fee31680a6d5..a65
From: Jie Zhang
Add gpu and gmu nodes for qcs8300 chipset.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 93 +++
1 file changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
b/arch
From: Jie Zhang
Enable GPU for qcs8300-ride platform and provide path for zap
shader.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
b
From: Jie Zhang
Add support for Adreno 623 GPU found in QCS8300 chipsets.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8
drivers/gpu/drm/msm
From: Jie Zhang
Document Adreno 623 GMU in the dt-binding specification.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm
From: Jie Zhang
Adreno 621 has a different memory map for GPUCC block. So update
a6xx_gpu_state code to dump the correct set of gpucc registers.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 13 ++---
drivers/gpu/drm/msm
On 2/12/2025 4:26 PM, Dmitry Baryshkov wrote:
> On Wed, Feb 12, 2025 at 12:48:01PM +0530, Akhil P Oommen wrote:
>> On 2/12/2025 5:30 AM, Dmitry Baryshkov wrote:
>>> On Tue, Feb 11, 2025 at 06:41:39PM +0530, Akhil P Oommen wrote:
>>>> On 2/9/2025 9:59 PM, Dmitry Bary
On 2/12/2025 5:30 AM, Dmitry Baryshkov wrote:
> On Tue, Feb 11, 2025 at 06:41:39PM +0530, Akhil P Oommen wrote:
>> On 2/9/2025 9:59 PM, Dmitry Baryshkov wrote:
>>> On Wed, Nov 13, 2024 at 02:18:43AM +0530, Akhil P Oommen wrote:
>>>> On 10/30/2024 12:32 PM, Akhil P Oom
On 2/13/2025 10:24 PM, Dmitry Baryshkov wrote:
> On Thu, Feb 13, 2025 at 09:40:07PM +0530, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add support for Adreno 623 GPU found in QCS8300 chipsets.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P
On 3/15/2025 12:04 AM, Rob Clark wrote:
> From: Rob Clark
>
> IB_SIZE is only b0..b19. Starting with a6xx gen3, additional fields
> were added above the IB_SIZE. Accidentially setting them can cause
> badness. Fix this by properly defining the CP_INDIRECT_BUFFER packet
> and using the generate
On 2/28/2025 1:37 AM, Akhil P Oommen wrote:
> This series adds support for A623 GPU found in QCS8300 chipsets. This
> GPU IP is very similar to A621 GPU, except for the UBWC configuration
> and the GMU firmware.
>
> Both DT patches are for Bjorn and rest of the patches for Rob Cla
On 4/18/2025 6:40 AM, Connor Abbott wrote:
> On Thu, Apr 17, 2025, 1:50 PM Akhil P Oommen wrote:
>>
>> On 4/17/2025 9:02 PM, Connor Abbott wrote:
>>> On Thu, Apr 17, 2025 at 3:45 AM Akhil P Oommen
>>> wrote:
>>>>
>>>> On 4/10/2025
On 4/17/2025 9:02 PM, Connor Abbott wrote:
> On Thu, Apr 17, 2025 at 3:45 AM Akhil P Oommen
> wrote:
>>
>> On 4/10/2025 11:13 PM, Konrad Dybcio wrote:
>>> From: Konrad Dybcio
>>>
>>> The Highest Bank address Bit value can change based on mem
On 4/23/2025 5:27 AM, Konrad Dybcio wrote:
> On 4/21/25 10:13 PM, Rob Clark wrote:
>> On Fri, Apr 18, 2025 at 9:00 AM Akhil P Oommen
>> wrote:
>>>
>>> On 4/18/2025 6:40 AM, Connor Abbott wrote:
>>>> On Thu, Apr 17, 2025, 1:50 PM Akhil P Oommen
On 3/19/2025 8:22 PM, Rob Clark wrote:
> From: Rob Clark
>
> It is standing in the way of drm_gpuvm / VM_BIND support. Not to
> mention frequently broken and rarely tested. And I think only needed
> for a 10yr old not quite upstream SoC (msm8974).
>
> Maybe we can add support back in later, bu
On 3/19/2025 8:22 PM, Rob Clark wrote:
> From: Rob Clark
>
> Now that we've realigned deletion and allocation, switch over to using
> drm_gpuvm/drm_gpuva. This allows us to support multiple VMAs per BO per
> VM, to allow mapping different parts of a single BO at different virtual
> addresses, wh
On 3/19/2025 8:22 PM, Rob Clark wrote:
> From: Rob Clark
>
> In the next commit, a way for userspace to opt-in to userspace managed
> VM is added. For this to work, we need to defer creation of the VM
> until it is needed.
>
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/a6xx_g
On 4/10/2025 11:13 PM, Konrad Dybcio wrote:
> From: Konrad Dybcio
>
> The Highest Bank address Bit value can change based on memory type used.
>
> Attempt to retrieve it dynamically, and fall back to a reasonable
> default (the one used prior to this change) on error.
>
> Signed-off-by: Konrad
On 4/25/2025 2:35 PM, Konrad Dybcio wrote:
> On 7/15/24 10:04 PM, Akhil P Oommen wrote:
>> On Tue, Jul 09, 2024 at 12:45:29PM +0200, Konrad Dybcio wrote:
>>> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
>>> abstracted through SMEM, instead of be
On 4/30/2025 10:26 PM, neil.armstr...@linaro.org wrote:
> On 30/04/2025 18:39, Konrad Dybcio wrote:
>> On 4/30/25 6:19 PM, neil.armstr...@linaro.org wrote:
>>> On 30/04/2025 17:36, Konrad Dybcio wrote:
On 4/30/25 4:49 PM, neil.armstr...@linaro.org wrote:
> On 30/04/2025 15:09, Konrad Dybci
On 5/1/2025 12:10 AM, Rob Clark wrote:
> On Wed, Apr 30, 2025 at 3:39 AM Konrad Dybcio
> wrote:
>>
>> On 4/29/25 2:17 PM, Dmitry Baryshkov wrote:
>>> On Mon, Apr 28, 2025 at 11:19:32PM +0200, Konrad Dybcio wrote:
>>>> On 4/28/25 12:44 PM, Akhil P Oommen wr
On 4/14/2025 4:31 PM, Konrad Dybcio wrote:
> On 2/27/25 9:07 PM, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add gpu and gmu nodes for qcs8300 chipset.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P Oommen
>> ---
&
On 4/23/2025 6:58 PM, Dmitry Baryshkov wrote:
> On Sat, Apr 19, 2025 at 08:21:32PM +0530, Akhil P Oommen wrote:
>> Fix the following for qmp_get() errors:
>>
>> 1. Correctly handle probe defer for A6x GPUs
>> 2. Ignore other errors because those are okay when GPU ACD i
anges in v2:
- Removed RFC tag for the series
- Improve documentation for the new dt bindings (Krzysztof)
- Add fallback compatible string for opp-table (Krzysztof)
- Link to v1:
https://lore.kernel.org/r/20241012-gpu-acd-v1-0-1e5e91aa9...@quicinc.com
---
Akhil P Oommen (7):
drm/msm/adreno: Add
detected based on devicetree data.
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
Reviewed-by: Konrad Dybcio
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 84 ++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
drivers/gpu/drm/msm
Update GPU node to include acd level values.
Reviewed-by: Konrad Dybcio
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64
When ACD feature is enabled, it triggers some internal calibrations
which result in a pretty long delay during the first HFI perf vote.
So, increase the HFI response timeout to match the downstream driver.
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
Signed-off-by: Akhil P Oommen
Add a module param to disable ACD which will help to quickly rule it
out for any GPU issues.
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
Reviewed-by: Konrad Dybcio
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 +++
drivers/gpu/drm/msm/adreno
AINTAINERS file include the new opp-v2-qcom-adreno.yaml.
Cc: Rob Clark
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Akhil P Oommen
---
.../bindings/opp/opp-v2-qcom-adreno.yaml | 96
Now that we have ACD support for GPU, add additional OPPs up to
Turbo L3 which are supported across all existing SKUs.
Reviewed-by: Konrad Dybcio
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 16
-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index
6bd6d7c67f98b38cb1d23f926b5e6ccbd7f2ec53
On 1/9/2025 2:10 AM, Akhil P Oommen wrote:
> Add a new schema which extends opp-v2 to support a new vendor specific
> property required for Adreno GPUs found in Qualcomm's SoCs. The new
> property called "qcom,opp-acd-level" carries a u32 value recommended
> for each op
AINTAINERS file include the new opp-v2-qcom-adreno.yaml.
Cc: Rob Clark
Signed-off-by: Akhil P Oommen
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
---
.../bindings/opp/opp-v2-qcom-adreno.yaml | 96 ++
MAINTAINERS| 1 +
Update GPU node to include acd level values.
Signed-off-by: Akhil P Oommen
Reviewed-by: Konrad Dybcio
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64
or opp-table (Krzysztof)
- Link to v1:
https://lore.kernel.org/r/20241012-gpu-acd-v1-0-1e5e91aa9...@quicinc.com
---
Akhil P Oommen (7):
drm/msm/adreno: Add support for ACD
drm/msm/a6xx: Increase HFI response timeout
drm/msm: a6x: Rework qmp_get() error handling
drm/msm/adr
detected based on devicetree data.
Signed-off-by: Akhil P Oommen
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 84 ++-
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 36
When ACD feature is enabled, it triggers some internal calibrations
which result in a pretty long delay during the first HFI perf vote.
So, increase the HFI response timeout to match the downstream driver.
Signed-off-by: Akhil P Oommen
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
Add a module param to disable ACD which will help to quickly rule it
out for any GPU issues.
Signed-off-by: Akhil P Oommen
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 +++
drivers/gpu/drm/msm/adreno/adreno_device.c | 4
2
Fix the following for qmp_get() errors:
1. Correctly handle probe defer for A6x GPUs
2. Ignore other errors because those are okay when GPU ACD is
not required. They are checked again during gpu acd probe.
Signed-off-by: Akhil P Oommen
Reviewed-by: Konrad Dybcio
Tested-by: Maya Matuszczyk
Now that we have ACD support for GPU, add additional OPPs up to
Turbo L3 which are supported across all existing SKUs.
Signed-off-by: Akhil P Oommen
Reviewed-by: Konrad Dybcio
Tested-by: Maya Matuszczyk
Tested-by: Anthony Ruhier
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 16
From: Jie Zhang
Some GPUs have different memory map for GPUCC block. So split out the
gpucc range from a6xx_gmu_cx_registers to a separate block to
accommodate those GPUs.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 8
From: Jie Zhang
Document Adreno 623 GMU in the dt-binding specification.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
Reviewed-by: Krzysztof Kozlowski
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation
-branch-gfx-smmu-b03261963064:v5
prerequisite-patch-id: f8fd1a2020c940e595e58a8bd3c55d00d3d87271
prerequisite-patch-id: 08a0540f75b0f95fd2018b38c9ed5c6f96433b4d
Best regards,
--
Akhil P Oommen
From: Jie Zhang
Adreno 621 has a different memory map for GPUCC block. So update
a6xx_gpu_state code to dump the correct set of gpucc registers.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 9 +++--
drivers/gpu/drm/msm/adreno
On 2/28/2025 4:56 AM, Dmitry Baryshkov wrote:
> On Fri, Feb 28, 2025 at 01:37:51AM +0530, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add support for Adreno 623 GPU found in QCS8300 chipsets.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P
On 2/28/2025 7:53 PM, Rob Herring (Arm) wrote:
>
> On Fri, 28 Feb 2025 01:37:48 +0530, Akhil P Oommen wrote:
>> This series adds support for A623 GPU found in QCS8300 chipsets. This
>> GPU IP is very similar to A621 GPU, except for the UBWC configuration
>> and the GMU
On 2/28/2025 1:59 AM, Konrad Dybcio wrote:
> On 27.02.2025 9:07 PM, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add support for Adreno 623 GPU found in QCS8300 chipsets.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P Oommen
>> ---
From: Jie Zhang
Add gpu and gmu nodes for qcs8300 chipset.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 93 +++
1 file changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
b/arch
From: Jie Zhang
Add support for Adreno 623 GPU found in QCS8300 chipsets.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8
drivers/gpu/drm/msm
From: Jie Zhang
Enable GPU for qcs8300-ride platform and provide path for zap
shader.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
Reviewed-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64
On 2/13/2025 10:26 PM, Dmitry Baryshkov wrote:
> On Thu, Feb 13, 2025 at 09:40:09PM +0530, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add gpu and gmu nodes for qcs8300 chipset.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P Oommen
>>
On 2/13/2025 10:12 PM, Dmitry Baryshkov wrote:
> On Thu, Feb 13, 2025 at 09:40:05PM +0530, Akhil P Oommen wrote:
>
> Nit: subject needs to be fixed
That escaped my eyes. Will fix in the next rev.
-Akhil
>
>> This series adds support for A623 GPU found in QCS8300 chipsets.
-f6698603fb85
prerequisite-change-id: 20250131-b4-branch-gfx-smmu-b03261963064:v5
prerequisite-patch-id: f8fd1a2020c940e595e58a8bd3c55d00d3d87271
prerequisite-patch-id: 08a0540f75b0f95fd2018b38c9ed5c6f96433b4d
Best regards,
--
Akhil P Oommen
On 2/13/2025 10:06 PM, Konrad Dybcio wrote:
> On 13.02.2025 5:10 PM, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Adreno 621 has a different memory map for GPUCC block. So update
>> a6xx_gpu_state code to dump the correct set of gpucc registers.
>>
>> Sig
On 2/13/2025 10:51 PM, Konrad Dybcio wrote:
> On 13.02.2025 5:10 PM, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add support for Adreno 623 GPU found in QCS8300 chipsets.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P Oommen
>> ---
On 2/18/2025 11:52 PM, Rob Clark wrote:
> On Thu, Feb 13, 2025 at 8:10 AM Akhil P Oommen
> wrote:
>>
>> From: Jie Zhang
>>
>> Adreno 621 has a different memory map for GPUCC block. So update
>> a6xx_gpu_state code to dump the correct set of gpucc regis
e time),
> see https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25981.
> So let's go ahead and expose it now.
>
> Signed-off-by: Rob Clark
Reviewed-by: Akhil P Oommen
-Akhil
> ---
> drivers/gpu/drm/msm/msm_drv.c | 1 +
> 1 file changed, 1 insertion(+)
>
>
pend. Also, calling prepare-suspend without a prior oob-gpu handshake
messes up gmu firmware's internal state. So, do that when required.
Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support")
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/m
pend. Also, calling prepare-slumber without a prior oob-gpu handshake
messes up gmu firmware's internal state. So, do that when required.
Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support")
Cc: sta...@vger.kernel.org
Signed-off-by: Akhil P Oommen
---
Changes in v2:
- Minor update
From: Jie Zhang
Enable GPU for qcs8300-ride platform and provide path for zap
shader.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
Reviewed-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64
From: Jie Zhang
Add gpu and gmu nodes for qcs8300 chipset.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 91 +++
1 file changed, 91 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
b/arch
From: Jie Zhang
Add gpu and gmu nodes for qcs8300 chipset.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 91 +++
1 file changed, 91 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
b/arch
On 5/1/2025 9:23 PM, Konrad Dybcio wrote:
> On 5/1/25 11:29 AM, Akhil P Oommen wrote:
>> On 4/30/2025 10:26 PM, neil.armstr...@linaro.org wrote:
>>> On 30/04/2025 18:39, Konrad Dybcio wrote:
>>>> On 4/30/25 6:19 PM, neil.armstr...@linaro.org wrote:
>>>>
From: Jie Zhang
Document Adreno 623 GMU in the dt-binding specification.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
Reviewed-by: Krzysztof Kozlowski
---
.../devicetree/bindings/display/msm/gmu.yaml | 34 ++
1 file changed, 34 insertions(+)
diff --git a
tch-id: 6a64b525e8ef33377b3cd885554b421fe8e6a192
Best regards,
--
Akhil P Oommen
On 5/9/2025 11:12 AM, Krzysztof Kozlowski wrote:
> On 08/05/2025 18:19, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Document Adreno 623 GMU in the dt-binding specification.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P Oommen
>> Rev
: 20250213-a623-gpu-support-f6698603fb85
prerequisite-message-id:
<20250310-b4-branch-gfx-smmu-v6-2-15c60b8ab...@quicinc.com>
prerequisite-patch-id: f8fd1a2020c940e595e58a8bd3c55d00d3d87271
prerequisite-patch-id: 6a64b525e8ef33377b3cd885554b421fe8e6a192
Best regards,
--
Akhil P Oommen
On 5/9/2025 11:14 AM, Krzysztof Kozlowski wrote:
> On 08/05/2025 18:19, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Enable GPU for qcs8300-ride platform and provide path for zap
>> shader.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akh
From: Jie Zhang
Update Adreno 623's dt-binding to remove smmu_clk which is not required
for this GMU.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
.../devicetree/bindings/display/msm/gmu.yaml | 34 ++
1 file changed, 34 insertions(+)
diff --
From: Jie Zhang
Enable GPU for qcs8300-ride platform and provide path for zap
shader.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
Reviewed-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64
On 5/13/2025 2:18 AM, Konrad Dybcio wrote:
> On 5/9/25 9:21 AM, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add gpu and gmu nodes for qcs8300 chipset.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P Oommen
>> ---
>
&
On 6/8/2025 8:51 PM, Rob Clark wrote:
> On Sat, Jun 7, 2025 at 7:15 AM Akhil P Oommen
> wrote:
>>
>> Add support for X1-45 GPU found in X1P41200 chipset (8 cpu core
>> version). X1-45 is a smaller version of X1-85 with lower core count and
>> smaller memories.
X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller
version of Adreno X1-85 GPU. Describe this new GPU and also add
the secure gpu firmware path that should used for X1P42100 CRD.
Tested-by: Jens Glathe
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi
Add support for Adreno X1-45 GPU present Snapdragon X1P42100
series of compute chipsets. This GPU is a smaller version of
X1-85 GPU with lower core count and smaller internal memories.
Reviewed-by: Konrad Dybcio
Reviewed-by: Dmitry Baryshkov
Tested-by: Jens Glathe
Signed-off-by: Akhil P Oommen
n can pick the DT patch and Rob Clark can pick up the rest.
Signed-off-by: Akhil P Oommen
---
Changes in v3:
- Rebased on v6.16-rc1
- Fixed speedbin table in drm/msm
- Corrected the regex for the adreno opp node (Krzysztof)
- Replace underscore with hypen in DT node names (Krzysztof)
- Link
In order to enable GPU support in X1P42100-CRD and other similar
laptops with Snapdragon X1P42100 SoC, enable X1P42100 GPUCC driver
as a module.
Tested-by: Jens Glathe
Signed-off-by: Akhil P Oommen
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64
Fmax */
opp-66600-1 {
opp-hz = /bits/ 64 <66600>;
opp-level = ;
opp-peak-kBps = <1650>;
qcom,opp-acd-level = <0xa82d5ffd>;
opp-supported-hw = <0x10>;
};
Update the regex to allow this usecase.
Tested-by: Jens Glathe
S
n can pick the DT patch and Rob Clark can pick up the rest.
Signed-off-by: Akhil P Oommen
---
Changes in v4:
- Reorder the new entry in defconfig (Krzysztof)
- Link to v3:
https://lore.kernel.org/r/20250620-x1p-adreno-v3-0-56398c078...@oss.qualcomm.com
Changes in v3:
- Rebased on v6.16-rc1
-
In order to enable GPU support in X1P42100-CRD and other similar
laptops with Snapdragon X1P42100 SoC, enable X1P42100 GPUCC driver
as a module.
Signed-off-by: Akhil P Oommen
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch
Vinarskis # x1-26-100
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index
: Viresh Kumar
Reviewed-by: Krzysztof Kozlowski
Tested-by: Aleksandrs Vinarskis # x1-26-100
Signed-off-by: Akhil P Oommen
---
Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/opp/opp
-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi| 7 ++
arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 +
arch/arm64/boot/dts/qcom/x1p42100.dtsi| 120 +-
3 files changed, 129 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts
On 6/12/2025 4:59 PM, Krzysztof Kozlowski wrote:
> On 11/06/2025 14:24, Akhil P Oommen wrote:
>>>>
>>>> patternProperties:
>>>> - '^opp-[0-9]+$':
>>>> + '^opp(-?[0-9]+)*$':
>>>
>>> Not correct regex.
On 6/15/2025 12:12 AM, Konrad Dybcio wrote:
> On 6/12/25 11:19 PM, Akhil P Oommen wrote:
>> On 6/12/2025 5:32 PM, Jens Glathe wrote:
>>> On 6/11/25 13:15, Akhil P Oommen wrote:
>>>
>>>> Add support for X1-45 GPU found in X1P41200 chipset (8 cpu core
>>
X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller
version of Adreno X1-85 GPU. Describe this new GPU and also add
the secure gpu firmware path that should used for X1P42100 CRD.
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi| 7 ++
arch/arm64/boot
ff-by: Akhil P Oommen
---
Akhil P Oommen (3):
arm64: defconfig: Enable X1P42100_GPUCC driver
drm/msm/adreno: Add Adreno X1-45 support
arm64: dts: qcom: Add GPU support to X1P42100 SoC
arch/arm64/boot/dts/qcom/x1e80100.dtsi| 7 ++
arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4
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