On Fri, Feb 14, 2025 at 01:57:45AM +0200, Laurent Pinchart wrote:
> Hi Dmitry,
>
> Thank you for the patch.
>
> On Sun, Feb 09, 2025 at 03:41:18PM +0200, Dmitry Baryshkov wrote:
> > DRM HDMI Codec framework is useful not only for the HDMI bridges, but
> > also for the DisplayPort bridges. Add new
SDM845 Type-C DisplayPort output inactive on DP Monitor and tears on HDMI.
During testing and research found that the dp and dpu drivers more
closely match later incarnations of the Android driver.
Compared against the 4.9 Android and found the porch timing and
wide bus elements were disabled.
Tes
Type-C DisplayPort inoperable due to incorrect porch settings.
- Re-used wide_bus_en as flag to prevent porch shifting
Fixes: c943b4948b58 ("drm/msm/dp: add displayPort driver support")
Signed-off-by: James A. MacInnes
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 14 +-
SDM845 DPU hardware is rev 4.0.0 per hardware documents.
Original patch to enable wide_bus operation did not take into account
the SDM845 and it got carried over by accident.
- Incorrect setting caused inoperable DisplayPort.
- Corrected by separating SDM845 into its own descriptor.
Fixes: c7c412
From: Jie Zhang
Add gpu and gmu nodes for qcs8300 chipset.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 93 +++
1 file changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
b/arch/ar
From: Jie Zhang
Enable GPU for qcs8300-ride platform and provide path for zap
shader.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts
b/a
From: Jie Zhang
Add support for Adreno 623 GPU found in QCS8300 chipsets.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8
drivers/gpu/drm/msm/a
From: Jie Zhang
Document Adreno 623 GMU in the dt-binding specification.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
From: Jie Zhang
Adreno 621 has a different memory map for GPUCC block. So update
a6xx_gpu_state code to dump the correct set of gpucc registers.
Signed-off-by: Jie Zhang
Signed-off-by: Akhil P Oommen
---
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 13 ++---
drivers/gpu/drm/msm/adren
Hi
Am 13.02.25 um 17:35 schrieb Abel Vesa:
On 24-12-19 23:36:56, Konrad Dybcio wrote:
From: Konrad Dybcio
Log the version for informational purposes, such as for keeping track
of possible GMU fw-related failures in crash / CI logs.
Intentionally not implemented on the if (gmu->legacy) codepa
On 2/12/2025 4:26 PM, Dmitry Baryshkov wrote:
> On Wed, Feb 12, 2025 at 12:48:01PM +0530, Akhil P Oommen wrote:
>> On 2/12/2025 5:30 AM, Dmitry Baryshkov wrote:
>>> On Tue, Feb 11, 2025 at 06:41:39PM +0530, Akhil P Oommen wrote:
On 2/9/2025 9:59 PM, Dmitry Baryshkov wrote:
> On Wed, Nov 13
On Thu, Feb 13, 2025 at 05:27:58PM +0100, Neil Armstrong wrote:
> The bindings requires the mdp0-mem and the cpu-cfg interconnect path,
> add the missing cpu-cfg path to fix the dtbs check error.
I'd say that this is not just to 'fix dtbs check', but also to ensure
that MDSS has enough bandwidth t
On 13.02.2025 5:41 PM, Thomas Zimmermann wrote:
> Hi
>
> Am 13.02.25 um 17:35 schrieb Abel Vesa:
>> On 24-12-19 23:36:56, Konrad Dybcio wrote:
>>> From: Konrad Dybcio
>>>
>>> Log the version for informational purposes, such as for keeping track
>>> of possible GMU fw-related failures in crash / C
On 2/13/2025 10:26 PM, Dmitry Baryshkov wrote:
> On Thu, Feb 13, 2025 at 09:40:09PM +0530, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Add gpu and gmu nodes for qcs8300 chipset.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by: Akhil P Oommen
>> ---
>> arch/arm64/boot/dts/qcom/qcs8300.dtsi |
On Thu, Feb 13, 2025 at 8:36 AM Konrad Dybcio
wrote:
>
> On 13.02.2025 5:10 PM, Akhil P Oommen wrote:
> > From: Jie Zhang
> >
> > Adreno 621 has a different memory map for GPUCC block. So update
> > a6xx_gpu_state code to dump the correct set of gpucc registers.
> >
> > Signed-off-by: Jie Zhang
On 13.02.2025 5:10 PM, Akhil P Oommen wrote:
> From: Jie Zhang
>
> Add support for Adreno 623 GPU found in QCS8300 chipsets.
>
> Signed-off-by: Jie Zhang
> Signed-off-by: Akhil P Oommen
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29
> +
> drivers/gpu/dr
On 13.02.2025 6:19 PM, Rob Clark wrote:
> On Thu, Feb 13, 2025 at 8:36 AM Konrad Dybcio
> wrote:
>>
>> On 13.02.2025 5:10 PM, Akhil P Oommen wrote:
>>> From: Jie Zhang
>>>
>>> Adreno 621 has a different memory map for GPUCC block. So update
>>> a6xx_gpu_state code to dump the correct set of gpucc
The mdp1-mem is not supported on the SM8550 SoCs, and having maxItems=2
makes the bindings not clear if mdp0-mem/mdp1-mem or mdp0-mem/cpu-cfg is
required, so explicitly document the mdp0-mem/cpu-cfg interconnect and
add the cpu-cfg path in the example.
Suggested-by: Dmitry Baryshkov
Reviewed-by:
On Thu, Feb 13, 2025 at 05:27:59PM +0100, Neil Armstrong wrote:
> The bindings requires the mdp0-mem and the cpu-cfg interconnect path,
> add the missing cpu-cfg path to fix the dtbs check error.
Same comment. Nevertheless
Reviewed-by: Dmitry Baryshkov
>
> Fixes: 9fa33cbca3d2 ("arm64: dts: qc
The bindings requires the mdp0-mem and the cpu-cfg interconnect path,
add the missing cpu-cfg path to fix the dtbs check error.
Fixes: 9fa33cbca3d2 ("arm64: dts: qcom: sm8650: correct MDSS interconnects")
Reviewed-by: Konrad Dybcio
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/qcom/sm86
; drivers/gpu/drm/msm/adreno/adreno_gpu.h| 5 ++
> 8 files changed, 171 insertions(+), 3 deletions(-)
> ---
> base-commit: 6a25088d268ce4c2163142ead7fe1975bb687cb7
> change-id: 20250213-a623-gpu-support-f6698603fb85
> prerequisite-change-id: 20250131-b4-branch-gfx
9 +++
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++
>> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c| 13 ++-
>> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h| 17
>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++
>> 8 fil
0;
}
---
base-commit: df5d6180169ae06a2eac57e33b077ad6f6252440
change-id: 20250213-topic-gmu_no_spam-4fc4c459755d
Best regards,
Reviewed-by: Neil Armstrong
On Thu, Feb 13, 2025 at 09:40:10PM +0530, Akhil P Oommen wrote:
> From: Jie Zhang
>
> Enable GPU for qcs8300-ride platform and provide path for zap
> shader.
>
> Signed-off-by: Jie Zhang
> Signed-off-by: Akhil P Oommen
> ---
> arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 8
> 1 file c
The mdp1-mem is not supported on the SM8550 & SM8650 SoCs, so properly document
the mdp0-mem and cpu-cfg interconnect entries.
This fixes the following errors:
display-subsystem@ae0: interconnects: [[200, 3, 7, 32, 1, 7]] is too short
from schema $id:
http://devicetree.org/schemas/dis
FIELD_GET(A6XX_GMU_CORE_FW_VERSION_MAJOR__MASK, ver),
+ FIELD_GET(A6XX_GMU_CORE_FW_VERSION_MINOR__MASK, ver),
+ FIELD_GET(A6XX_GMU_CORE_FW_VERSION_STEP__MASK, ver));
return 0;
}
---
base-commit: df5d6180169ae06a2eac57e33b077ad6f62
The mdp1-mem is not supported on the SM8550 SoCs, and having maxItems=2
makes the bindings not clear if mdp0-mem/mdp1-mem or mdp0-mem/cpu-cfg
is required, so explicitly document the mdp0-mem/cpu-cfg interconnect
paths and complete the example with the missing interconnect paths.
Suggested-by: Dmit
The bindings requires the mdp0-mem and the cpu-cfg interconnect path,
add the missing cpu-cfg path to fix the dtbs check error.
Fixes: b8591df49cde ("arm64: dts: qcom: sm8550: correct MDSS interconnects")
Reviewed-by: Konrad Dybcio
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/qcom/sm85
On Thu, Feb 13, 2025 at 09:40:07PM +0530, Akhil P Oommen wrote:
> From: Jie Zhang
>
> Add support for Adreno 623 GPU found in QCS8300 chipsets.
>
> Signed-off-by: Jie Zhang
> Signed-off-by: Akhil P Oommen
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 29
>
/a6xx_gpu_state.c| 13 ++-
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h| 17
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 5 ++
8 files changed, 171 insertions(+), 3 deletions(-)
---
base-commit: 6a25088d268ce4c2163142ead7fe1975bb687cb7
change-id: 20250213-a623-gpu-support
On 24-12-19 23:36:56, Konrad Dybcio wrote:
> From: Konrad Dybcio
>
> Log the version for informational purposes, such as for keeping track
> of possible GMU fw-related failures in crash / CI logs.
>
> Intentionally not implemented on the if (gmu->legacy) codepath, as
> these registers seem not t
On 13.02.2025 5:10 PM, Akhil P Oommen wrote:
> From: Jie Zhang
>
> Adreno 621 has a different memory map for GPUCC block. So update
> a6xx_gpu_state code to dump the correct set of gpucc registers.
>
> Signed-off-by: Jie Zhang
> Signed-off-by: Akhil P Oommen
> ---
So GPU_CC is outside what we
On 2/13/2025 10:06 PM, Konrad Dybcio wrote:
> On 13.02.2025 5:10 PM, Akhil P Oommen wrote:
>> From: Jie Zhang
>>
>> Adreno 621 has a different memory map for GPUCC block. So update
>> a6xx_gpu_state code to dump the correct set of gpucc registers.
>>
>> Signed-off-by: Jie Zhang
>> Signed-off-by:
On Thu, Feb 13, 2025 at 09:40:09PM +0530, Akhil P Oommen wrote:
> From: Jie Zhang
>
> Add gpu and gmu nodes for qcs8300 chipset.
>
> Signed-off-by: Jie Zhang
> Signed-off-by: Akhil P Oommen
> ---
> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 93
> +++
> 1 file cha
Hi Dmitry,
Thank you for the patch.
On Sun, Feb 09, 2025 at 03:41:18PM +0200, Dmitry Baryshkov wrote:
> DRM HDMI Codec framework is useful not only for the HDMI bridges, but
> also for the DisplayPort bridges. Add new DRM_BRIDGE_OP_DisplayPort
> define in order to distinguish DP bridges. Create H
35 matches
Mail list logo
