Re: [PATCH v3 9/9] arm64: dts: qcom: Add display support for QCS615 RIDE board

On 2024/11/26 6:08, Dmitry Baryshkov wrote: On Mon, 25 Nov 2024 at 09:39, fange zhang wrote: On 2024/11/22 18:22, Dmitry Baryshkov wrote: On Fri, Nov 22, 2024 at 05:56:52PM +0800, Fange Zhang wrote: From: Li Liu Add display MDSS and DSI configuration for QCS615 RIDE board. QCS615 has

[PATCH 3/8] phy: qcom: qmp-usbc: Add DP phy mode support on QCS615

Extended DP support for QCS615 USB or DP phy. Differentiated between USBC and DP PHY using the match table’s type, dynamically generating different types of cfg and layout attributes during initialization based on this type. Static variables are stored in cfg, while parsed values are organized into

[PATCH 7/8] drm/msm/dp: Retry Link Training 2 with lower pattern

Add a mechanism to retry Link Training 2 by lowering the pattern level when the link training #2 first attempt fails. This approach enhances compatibility, particularly addressing issues caused by certain hub configurations. Signed-off-by: Xiangxu Yin --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 34 ++

[PATCH 5/8] drm/msm/dp: Add support for lane mapping configuration

Add the ability to configure lane mapping for the DP controller. This is required when the platform's lane mapping does not follow the default order (0, 1, 2, 3). The mapping rules are now configurable via the `data-lane` property in the devicetree. This property defines the logical-to-physical lan

[PATCH 4/8] drm/msm/dp: Add DisplayPort support for QCS615

The Qualcomm QCS615 platform comes with a DisplayPort controller use the same base offset as sc7180. add support for this in DP driver. Signed-off-by: Xiangxu Yin --- drivers/gpu/drm/msm/dp/dp_display.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/dr

[PATCH 1/8] dt-bindings: display/msm: Document DP on QCS615

Document the DP hardware found on the Qualcomm QCS615 platform. Signed-off-by: Xiangxu Yin --- .../devicetree/bindings/display/msm/dp-controller.yaml | 13 + 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Docume

[PATCH 0/8] Add DisplayPort support for QCS615 platform

This series aims to extend the USB-C PHY to support DP mode and enable DisplayPort on the Qualcomm QCS615 platform. The devicetree modification for DisplayPort on QCS615 will be provided in a future patch. Signed-off-by: Xiangxu Yin --- Xiangxu Yin (8): dt-bindings: display/msm: Document D

[PATCH 2/8] dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: Add DP support for QCS615

Declare the DP QMP PHY present on the Qualcomm QCS615 platforms. Signed-off-by: Xiangxu Yin --- .../bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 21 +++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-u

[PATCH 6/8] drm/msm/dp: Add maximum width limitation for modes

Introduce a maximum width constraint for modes during validation. This ensures that the modes are filtered based on hardware capabilities, specifically addressing the line buffer limitations of individual pipes. Signed-off-by: Xiangxu Yin --- drivers/gpu/drm/msm/dp/dp_display.c | 3 +++ drivers

[PATCH v3 2/7] drm/msm: adreno: add plumbing to generate bandwidth vote table for GMU

The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along the Frequency and Power Domain level, but by default we leave the OPP core scale the interconnect ddr path. While scaling via the interconnect path was sufficient, newer GPUs like the A750 requires specific vote paremeters and

[PATCH v3 7/7] arm64: qcom: dts: sm8650: add interconnect and opp-peak-kBps for GPU

Each GPU OPP requires a specific peak DDR bandwidth, let's add those to each OPP and also the related interconnect path. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 ++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi

[PATCH v3 6/7] arm64: qcom: dts: sm8550: add interconnect and opp-peak-kBps for GPU

Each GPU OPP requires a specific peak DDR bandwidth, let's add those to each OPP and also the related interconnect path. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 11 +++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b

[PATCH v3 0/7] drm/msm: adreno: add support for DDR bandwidth scaling via GMU

voted for a same OPP, whatever decision is done by the GMU, it will ensure all resources votes are synchronized. Depends on [1] to avoid crashing when getting OPP bandwidths. [1] https://lore.kernel.org/all/20241128-topic-opp-fix-assert-index-check-v1-0-cb8bd4c03...@linaro.org/ Ran full vulkan-cts

[PATCH v3 5/7] drm/msm: adreno: enable GMU bandwidth for A740 and A750

Now all the DDR bandwidth voting via the GPU Management Unit (GMU) is in place, declare the Bus Control Modules (BCMs) and the corresponding parameters in the GPU info struct and add the GMU_BW_VOTE feature bit to enable it. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_catal

[PATCH v3 3/7] drm/msm: adreno: dynamically generate GMU bw table

The Adreno GPU Management Unit (GMU) can also scale the ddr bandwidth along the frequency and power domain level, but for now we statically fill the bw_table with values from the downstream driver. Only the first entry is used, which is a disable vote, so we currently rely on scaling via the linux

[PATCH v3 4/7] drm/msm: adreno: find bandwidth index of OPP and set it along freq index

The Adreno GPU Management Unit (GMU) can also scale the DDR Bandwidth along the Frequency and Power Domain level, until now we left the OPP core scale the OPP bandwidth via the interconnect path. In order to enable bandwidth voting via the GPU Management Unit (GMU), when an opp is set by devfreq w

[PATCH v3 1/7] drm/msm: adreno: add defines for gpu & gmu frequency table sizes

Even if the code uses ARRAY_SIZE() to fill those tables, it's still a best practice to not use magic values for tables in structs. Suggested-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 11 +++ 1 file changed, 7 insertions(+), 4 deletion

Re: [PATCH v3 1/7] drm/msm: adreno: add defines for gpu & gmu frequency table sizes

On Thu, Nov 28, 2024 at 11:25:41AM +0100, Neil Armstrong wrote: > Even if the code uses ARRAY_SIZE() to fill those tables, > it's still a best practice to not use magic values for > tables in structs. > > Suggested-by: Dmitry Baryshkov > Signed-off-by: Neil Armstrong > --- > drivers/gpu/drm/msm

Re: [PATCH v3 6/7] arm64: qcom: dts: sm8550: add interconnect and opp-peak-kBps for GPU

On Thu, Nov 28, 2024 at 11:25:46AM +0100, Neil Armstrong wrote: > Each GPU OPP requires a specific peak DDR bandwidth, let's add > those to each OPP and also the related interconnect path. > > Signed-off-by: Neil Armstrong > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 11 +++ > 1 file c

Re: [PATCH v3 7/7] arm64: qcom: dts: sm8650: add interconnect and opp-peak-kBps for GPU

On Thu, Nov 28, 2024 at 11:25:47AM +0100, Neil Armstrong wrote: > Each GPU OPP requires a specific peak DDR bandwidth, let's add > those to each OPP and also the related interconnect path. > > Signed-off-by: Neil Armstrong > --- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 ++ > 1 fil

Re: [PATCH v3 5/7] drm/msm: adreno: enable GMU bandwidth for A740 and A750

On Thu, Nov 28, 2024 at 11:25:45AM +0100, Neil Armstrong wrote: > Now all the DDR bandwidth voting via the GPU Management Unit (GMU) > is in place, declare the Bus Control Modules (BCMs) and the > corresponding parameters in the GPU info struct and add the > GMU_BW_VOTE feature bit to enable it. >

Re: [PATCH v3 6/7] arm64: qcom: dts: sm8550: add interconnect and opp-peak-kBps for GPU

On 28/11/2024 14:26, Dmitry Baryshkov wrote: On Thu, Nov 28, 2024 at 11:25:46AM +0100, Neil Armstrong wrote: Each GPU OPP requires a specific peak DDR bandwidth, let's add those to each OPP and also the related interconnect path. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8