From: Dmitry Baryshkov
Since DPU 5.0 CTL blocks do not require DPU_CTL_SPLIT_DISPLAY, as single
CTL is used for both interfaces. As both RM and encoder now handle
active CTLs, drop that feature bit.
Reviewed-by: Marijn Suijten
Tested-by: Neil Armstrong # on SM8550-QRD
Signed-off-by: Dmitry Bar
From: Dmitry Baryshkov
Switch drm_dp_helper.c to use new set of DPCD read / write helpers.
Reviewed-by: Lyude Paul
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dp_helper.c | 296 +---
1 file changed, 116 insertions(+), 180
From: Dmitry Baryshkov
In case of complex pipelines (e.g. the forthcoming quad-pipe) the DPU
might use more that one MERGE_3D block for a single output. Follow the
pattern and extend the CTL_MERGE_3D_ACTIVE active register instead of
simply writing new value there. Currently at most one MERGE_3D
From: Dmitry Baryshkov
Now as we have dropped the DPU_CTL_SPLIT_DISPLAY from DPU >= 5.0
configuration, drop the rm->has_legacy_ctl condition which short-cutted
the check for those platforms.
Suggested-by: Marijn Suijten
Reviewed-by: Marijn Suijten
Tested-by: Neil Armstrong # on SM8550-QRD
Sig
From: Dmitry Baryshkov
Unlike previous generation, since DPU 5.0 it is possible to use just one
CTL to handle all INTF and WB blocks for a single output. And one has to
use single CTL to support bonded DSI config. Allocate single CTL for
these DPU versions.
Reviewed-by: Marijn Suijten
Tested-by
From: Dmitry Baryshkov
Active controls require setup of the master interface. Pass the selected
interface to CTL configuration.
Reviewed-by: Marijn Suijten
Tested-by: Neil Armstrong # on SM8550-QRD
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +
From: Dmitry Baryshkov
If several interfaces are being handled through a single CTL, a main
('master') INTF needs to be programmed into a separate register. Write
corresponding value into that register.
Co-developed-by: Marijn Suijten
Signed-off-by: Marijn Suijten
Reviewed-by: Marijn Suijten
From: Dmitry Baryshkov
On DPU >= 5.0 CTL blocks were reworked in order to support using a
single CTL for all outputs. In preparation of reworking the RM code to
return single CTL make sure that dpu_encoder can cope with that.
Reviewed-by: Marijn Suijten
Tested-by: Neil Armstrong # on SM8550-QR
Since version 5.0 the DPU got an improved way of handling multi-output
configurations. It is now possible to program all pending changes
through a single CTL and flush everything at the same time.
Implement corresponding changes in the DPU driver.
Signed-off-by: Dmitry Baryshkov
---
Changes in v
From: Dmitry Baryshkov
The MSM DisplayPort driver implements several HDMI codec functions
in the driver, e.g. it manually manages HDMI codec device registration,
returning ELD and plugged_cb support. In order to reduce code
duplication reuse drm_hdmi_audio_* helpers and drm_bridge_connector
integ
On Thu, Mar 06, 2025 at 07:11:16PM +0100, Konrad Dybcio wrote:
> From: Konrad Dybcio
>
> The current compatible has been used with no corresponding
> documentation. Replace it with one that has been documented.
qcom,msm8916-kpss-acc is also not documented. Most likely you meant
qcom,kpss-acc-v2
A lot of DisplayPort bridges use HDMI Codec in order to provide audio
support. Present DRM HDMI Audio support has been written with the HDMI
and in particular DRM HDMI Connector framework support, however those
audio helpers can be easily reused for DisplayPort drivers too.
Patches by Hermes Wu th
On Thu, Mar 06, 2025 at 07:11:23PM +0100, Konrad Dybcio wrote:
> From: Konrad Dybcio
>
> The preemptively-merged node contains a property absent from the final
> bindings. Remove it.
>
> Signed-off-by: Konrad Dybcio
> ---
> arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 3 ---
> 1 file changed
On Thu, Mar 06, 2025 at 07:11:22PM +0100, Konrad Dybcio wrote:
> From: Konrad Dybcio
>
> The preemptively-merged node contains a property absent from the final
> bindings. Remove it.
>
> Signed-off-by: Konrad Dybcio
> ---
> arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi | 2 --
> 1 f
On Thu, Mar 06, 2025 at 07:11:18PM +0100, Konrad Dybcio wrote:
> From: Konrad Dybcio
>
> The node is currently named power-controller, which requires the device
> underneath is a power domain provider. Rename it to align with other
> SoCs and resolve this sort of warnings:
>
> power-controller@c
From: Dmitry Baryshkov
On Fri, 14 Feb 2025 16:14:23 -0800, Jessica Zhang wrote:
> DPU supports a single writeback session running concurrently with primary
> display when the CWB mux is configured properly. This series enables
> clone mode for DPU driver and adds support for programming the CWB
From: Dmitry Baryshkov
Switch drm_dp_tunnel.c to use new set of DPCD read / write helpers.
Reviewed-by: Lyude Paul
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dp_tunnel.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
d
From: Dmitry Baryshkov
On Wed, 26 Feb 2025 10:59:23 +0200, Dmitry Baryshkov wrote:
> This patchset sits on top Maxime's HDMI connector patchset ([1]).
>
> Currently this is an RFC exploring the interface between HDMI bridges
> and HDMI connector code. This has been lightly verified on the Qualc
From: Dmitry Baryshkov
On Sun, 09 Feb 2025 05:21:10 +0200, Dmitry Baryshkov wrote:
> Bring back a set of patches extracted from [1] per Abhinav's suggestion.
>
> Rework debugging overrides for the bandwidth and clock settings. Instead
> of specifying the 'mode' and some values, allow one to set
From: Dmitry Baryshkov
On Fri, 21 Feb 2025 16:13:11 +0100, Krzysztof Kozlowski wrote:
> The Qualcomm SA8775p MDSS display block comes with eDP phy, already used
> in DTS and already documented in phy/qcom,edp-phy.yaml binding. Add the
> missing device node in the binding and extend example to s
From: Dmitry Baryshkov
On Tue, 25 Feb 2025 10:30:26 +0300, Dan Carpenter wrote:
> If msm_gem_address_space_create() fails, then return right away.
> Otherwise it leads to a Oops when we dereference "aspace" on the next
> line.
>
>
Applied, thanks!
[1/1] drm/msm/dpu: fix error pointer derefer
From: Dmitry Baryshkov
On Thu, 23 Jan 2025 14:43:32 +0200, Dmitry Baryshkov wrote:
> As pointed out by Simona, the drm_atomic_helper_check_modeset() and
> drm_atomic_helper_check() require the former function is rerun if the
> driver's callbacks modify crtc_state->mode_changed. MSM is one of the
From: Dmitry Baryshkov
drm_dp_dpcd_read_link_status() follows the "return error code or number
of bytes read" protocol, with the code returning less bytes than
requested in case of some errors. However most of the drivers
interpreted that as "return error code in case of any error". Switch
drm_dp
From: Dmitry Baryshkov
Switch drm_dp_cec.c to use new set of DPCD read / write helpers.
Reviewed-by: Lyude Paul
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dp_cec.c | 37 ++--
1 file changed, 18 insertions(+), 19 delet
From: Dmitry Baryshkov
Switch drm_dp_aux_dev.c to use new set of DPCD read / write helpers.
Acked-by: Jani Nikula
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/display/drm_dp_aux_dev.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/displ
Existing DPCD access functions return an error code or the number of
bytes being read / write in case of partial access. However a lot of
drivers either (incorrectly) ignore partial access or mishandle error
codes. In other cases this results in a boilerplate code which compares
returned value with
On Fri, Mar 07, 2025 at 09:50:30AM +0800, Jiapeng Chong wrote:
> ./drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c: dpu_hw_cwb.h is included more
> than once.
>
> Reported-by: Abaci Robot
> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=19239
> Signed-off-by: Jiapeng Chong
> ---
> drivers/
On Thu, Mar 06, 2025 at 11:33:46AM -0800, Abhinav Kumar wrote:
>
>
> On 3/5/2025 10:44 PM, Dmitry Baryshkov wrote:
> > On Wed, Mar 05, 2025 at 07:16:51PM -0800, Jessica Zhang wrote:
> > > Similar to WB_MUX, CDM_MUX also needs to be adjusted to support
> > > dedicated CWB PINGPONGs
> > >
> > > Si
On Fri, Mar 07, 2025 at 09:50:30AM +0800, Jiapeng Chong wrote:
> ./drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c: dpu_hw_cwb.h is included more
> than once.
>
> Reported-by: Abaci Robot
> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=19239
> Signed-off-by: Jiapeng Chong
> ---
> drivers/
./drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c: dpu_hw_cwb.h is included more
than once.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=19239
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 1 -
1 file changed, 1 deletion(-)
diff
From: Konrad Dybcio
There's a separate path that allows register access from CPUSS.
Describe it.
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git
a/Documentation/devicetr
On 3/5/2025 10:44 PM, Dmitry Baryshkov wrote:
On Wed, Mar 05, 2025 at 07:16:51PM -0800, Jessica Zhang wrote:
Similar to WB_MUX, CDM_MUX also needs to be adjusted to support
dedicated CWB PINGPONGs
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 4 +++-
1 fil
On Tue, Feb 18, 2025 at 03:23:43PM +0100, Thomas Zimmermann wrote:
> Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
> buffer size. Align the pitch according to hardware requirements.
>
> Signed-off-by: Thomas Zimmermann
> Cc: Thierry Reding
> Cc: Mikko Perttunen
> ---
> dr
From: Konrad Dybcio
The preemptively-merged node contains a property absent from the final
bindings. Remove it.
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts
b/ar
From: Konrad Dybcio
Commit 53c6d854be4e ("dt-bindings: usb: dwc3: Clean up hs_phy_irq in binding")
reworked the dt-bindings to accurately represent the hardware.
Execute the second half of the cleanup by wiring up the missing
pwr_event IRQ and adjusting the entry order.
Signed-off-by: Konrad Dy
From: Konrad Dybcio
The current compatible has been used with no corresponding
documentation. Replace it with one that has been documented.
This has no functional effect, as these nodes' resources are only
consumed through a phandle reference, anyway.
Signed-off-by: Konrad Dybcio
---
arch/arm
From: Konrad Dybcio
MSM8916 seems to reuse the same hardware as MSM8974 and friends (for
whom this binding document was created). Add a new compatible for it.
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml | 4 +++-
1 file changed, 3 insertions(+
/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi | 2 --
10 files changed, 27 insertions(+), 22 deletions(-)
---
base-commit: 565351ae7e0cee80e9b5ed84452a5b13644ffc4d
change-id: 20250306-topic-dt_bindings_fixups-602d47c3c365
Best regards,
--
Konrad Dybcio
On Thu, Mar 06, 2025 at 03:04:50PM +0200, Jani Nikula wrote:
> On Thu, 06 Mar 2025, Jani Nikula wrote:
> > On Sat, 01 Mar 2025, Dmitry Baryshkov wrote:
> >> Existing DPCD access functions return an error code or the number of
> >> bytes being read / write in case of partial access. However a lot
On Wed, 5 Mar 2025 17:30:28 +0300
Dan Carpenter wrote:
> On Wed, Mar 05, 2025 at 02:17:32PM +, David Laight wrote:
...
> > And the 'fun' starts because NULL isn't required to use the all-zero
> > bit pattern.
> > Regardless of the bit-pattern, things like (void *)(1 - 1) are valid
> > NULL po
On Wed, 5 Mar 2025 11:51:59 +0300
Dan Carpenter wrote:
> On Wed, Mar 05, 2025 at 09:40:43AM +0100, Markus Elfring wrote:
> > >>> The address of a data structure member was determined before
> > >>> a corresponding null pointer check in the implementation of
> > >>> the functions “dpu_hw_pp_enable
On Sat, 01 Mar 2025, Dmitry Baryshkov wrote:
> Existing DPCD access functions return an error code or the number of
> bytes being read / write in case of partial access. However a lot of
> drivers either (incorrectly) ignore partial access or mishandle error
> codes. In other cases this results in
, 3 insertions(+), 2 deletions(-)
---
base-commit: 6d3175a72cc07e90f81fb35841048a8a9b5134cb
change-id: 20250306-dpu-fix-docs-3700642b33ea
Best regards,
--
Dmitry Baryshkov
On 05/03/2025 23:44, Dmitry Baryshkov wrote:
My Linaro email will stop working soon. Use @kernel.org email instead.
Signed-off-by: Dmitry Baryshkov
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index
29e1a423eee5bcf9df7938aaffe
On 05/03/2025 23:44, Dmitry Baryshkov wrote:
Remap all historical and non-historical entries to my kernel.org email.
Signed-off-by: Dmitry Baryshkov
---
.mailmap | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/.mailmap b/.mailmap
index
01145c078838bf9348e8d0e5e4
Fix a typo in struct dpu_encoder_virt kerneldoc, which made it ignore
description of the cwb_mask field.
Fixes: dd331404ac7c ("drm/msm/dpu: Configure CWB in writeback encoder")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
1 file changed, 1 insertion(+),
Correct commit 20972609d12c ("drm/msm/dpu: Require modeset if clone mode
status changes") and describe old_crtc_state and new_crtc_state params
instead of the single previously used parameter crtc_state.
Fixes: 20972609d12c ("drm/msm/dpu: Require modeset if clone mode status
changes")
Signed-off-
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