On 9/27/2023 3:01 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2023-09-25 09:07:18)
On 9/22/2023 6:35 PM, Abhinav Kumar wrote:
Doing link training when we get hpd instead of atomic_enable() is a
design choice we have been following for a while because for the case
when link training fails
On 9/27/2023 2:41 PM, Stephen Boyd wrote:
Quoting Abhinav Kumar (2023-09-22 18:35:27)
On 9/22/2023 2:54 PM, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2023-09-19 02:50:12)
This should be hpd_notify, who starts link training, not some event.
I think this driver should train the link du
On Sun, Jul 23, 2023 at 11:09 AM Marijn Suijten
wrote:
>
> Enable MDSS and DSI, and configure the Samsung SOFEF01-M ams597ut01
> 6.0" 1080x2520 panel.
>
> Reviewed-by: Konrad Dybcio
> Signed-off-by: Marijn Suijten
> ---
> .../dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 59
> ++
On Mon, 25 Sep 2023 19:26:29 -0400, Richard Acayan wrote:
> The SDM670 display controller has the same requirements as the SDM845
> display controller, despite having distinct properties as described in
> the catalog. Add the compatible for SDM670 to the SDM845 controller.
>
> Signed-off-by: Ric
On Mon, Sep 25, 2023 at 07:26:30PM -0400, Richard Acayan wrote:
> Add documentation for the SDM670 display subsystem, adapted from the
> SDM845 and SM6125 documentation.
>
> Signed-off-by: Richard Acayan
> ---
> .../display/msm/qcom,sdm670-mdss.yaml | 280 ++
> 1 file cha
On Mon, 25 Sep 2023 19:26:28 -0400, Richard Acayan wrote:
> The SDM670 has DSI ports. Add the compatible for the controller.
>
> Signed-off-by: Richard Acayan
> ---
> .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herr
The period to submit XDC 2024 hosting proposals has been extended and
the new deadline is **November 1, 2023**
Please, submit your proposals as soon as possible, thank you!
On Mon, 2023-06-19 at 15:43 +0200, Ricardo Garcia wrote:
> Hello everyone!
>
> The X.org board is soliciting proposals to h
Hi Kees,
On 9/22/23 14:32, Kees Cook wrote:
Prepare for the coming implementation by GCC and Clang of the __counted_by
attribute. Flexible array members annotated with __counted_by can have
their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS
(for array indexing) and CONFIG
On 28.09.2023 13:16, Dmitry Baryshkov wrote:
> From: Sandor Yu
>
> Allow HDMI PHYs to be configured through the generic
> functions through a custom structure added to the generic union.
>
> The parameters added here are based on HDMI PHY
> implementation practices. The current set of parameter
There are just two places where we set the bandwidth: in the resume and
in the suspend paths. Drop the wrapping function
msm_mdss_icc_request_bw() and call icc_set_bw() directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 19 ---
1 file changed, 8 insert
From: Konrad Dybcio
The DPU1 driver needs to handle all MDPn<->DDR paths, as well as
CPU<->SLAVE_DISPLAY_CFG. The former ones share how their values are
calculated, but the latter one has static predefines spanning all SoCs.
In preparation for supporting the CPU<->SLAVE_DISPLAY_CFG path, rename
Stop using hand-written reset function for ICC release, use
devm_of_icc_get() instead.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 16 ++--
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
another path that needs to be handled to ensure MDSS functions properly,
namely the "reg bus", a.k.a the CPU-MDSS interconnect.
Gating that path may have a variety of effects, from none to otherwise
inexplicable DSI timeouts.
Pro
From: Linus Torvalds
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index ceb23eed4dce..57698d048e2c 100644
--- a/Makefile
+++ b/Makefile
@@ -2,7 +2,7 @@
VERSION = 6
PATCHLEVEL = 6
SUBLEVEL = 0
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
NA
From: Konrad Dybcio
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there are
other connection paths:
- a path that connects rotator block to the DDR.
- a path that needs to be handled to ensure MDSS register access
functions properly, namely the "reg bus", a.k.a the CPU-MDSS CFG
Per agreement with Konrad, picked up this patch series.
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
another path that needs to be handled to ensure MDSS functions properly,
namely the "reg bus", a.k.a the CPU-MDSS interconnect.
Gating that path may have a variety of effect
Il 27/09/23 23:29, Adrián Larumbe ha scritto:
The drm-stats fdinfo tags made available to user space are drm-engine,
drm-cycles, drm-max-freq and drm-curfreq, one per job slot.
This deviates from standard practice in other DRM drivers, where a single
set of key:value pairs is provided for the wh
Il 27/09/23 23:29, Adrián Larumbe ha scritto:
These GPU registers will be used when programming the cycle counter, which
we need for providing accurate fdinfo drm-cycles values to user space.
Signed-off-by: Adrián Larumbe
Reviewed-by: Boris Brezillon
Reviewed-by: Steven Price
Reviewed-by: A
Il 27/09/23 23:29, Adrián Larumbe ha scritto:
A new DRM GEM object function is added so that drm_show_memory_stats can
provide more accurate memory usage numbers.
Ideally, in panfrost_gem_status, the BO's purgeable flag would be checked
after locking the driver's shrinker mutex, but drm_show_mem
Il 27/09/23 23:29, Adrián Larumbe ha scritto:
Some BO's might be mapped onto physical memory chunkwise and on demand,
like Panfrost's tiler heap. In this case, even though the
drm_gem_shmem_object page array might already be allocated, only a very
small fraction of the BO is currently backed by s
Il 27/09/23 23:29, Adrián Larumbe ha scritto:
BO's RSS is updated every time new pages are allocated on demand and mapped
for the object at GPU page fault's IRQ handler, but only for heap buffers.
The reason this is unnecessary for non-heap buffers is that they are mapped
onto the GPU's VA space
With the extp being the only "power" clock left, remove the surrounding
loops and handle the extp clock directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c| 24 ---
drivers/gpu/drm/msm/hdmi/hdmi.h| 6 +
drivers/gpu/drm/msm/hdmi/hdmi_
In consequent modeset calls, the atomic_pre_enable() will be called
several times without calling atomic_post_disable() inbetween. Thus
iframes will not be updated for the next mode. Fix this by setting the
iframe outside of the !power_on check.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/dr
In preparation to converting MSM HDMI driver to use PHY framework, which
requires phy_power_on() calls to be paired with phy_power_off(), add a
conditional call to msm_hdmi_phy_powerdown() before the call to
msm_hdmi_phy_powerup().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdm
In preparation of reworking the HDMI mode setting, switch pre_enable and
post_disable callbacks to their atomic variants.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/dr
The "uni" PLL is shared between several PHYS: APQ8064's SATA,
MSM8974/APQ8084 HDMI, MSM8916 DSI, MSM8974/APQ8084 DSI.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c | 23 +-
drivers/phy/qualcomm/phy-qcom-uniphy.h | 32
2 fi
Add support for HDMI PHY on Qualcomm MSM8x60 / APQ8060 platforms.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/Makefile | 1 +
drivers/phy/qualcomm/phy-qcom-hdmi-45nm.c | 184
drivers/phy/qualcomm/phy-qcom-hdmi-preqmp.c | 32 ++--
drivers/phy/q
Add the driver for pre-QMP Qualcomm HDMI PHYs. Currently it suppports
Qualcomm MSM8960 / APQ8064 platforms, other platforms will come later.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/Kconfig| 14 +
drivers/phy/qualcomm/Makefile | 6 +
drivers/phy/q
Drop source files used by old HDMI PHY and HDMI PLL drivers.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_phy.c | 216 ---
drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c | 51 --
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c | 765 ---
drivers/gpu/drm/msm/
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
index 62ce1455f974..fbcf4dd91cd9 100644
--- a/drivers/gpu/dr
Change the MSM HDMI driver to use generic PHY subsystem. Moving PHY
drivers allows better code sharing with the rest of the PHY system.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Makefile | 6 ---
drivers/gpu/drm/msm/hdmi/hdmi.c| 60 +++--
drivers/
Add support for HDMI PHY on Qualcomm MSM8974 / APQ8074 platforms.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/Kconfig| 2 +-
drivers/phy/qualcomm/Makefile | 1 +
drivers/phy/qualcomm/phy-qcom-hdmi-28hpm.c | 327
drivers/phy/qua
According to the vendor kernel [1] , the alt_iface clock should be
enabled together with the rest of HPD clocks, to make HPD to work
properly.
[1]
https://git.codelinaro.org/clo/la/kernel/msm-3.18/-/commit/e07a5487e521e57f76083c0a6e2f995414ac6d03
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry
Import register definitions from 28nm DSI and HDMI PHYs, adding more UNI
PHY registers.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualcomm/phy-qcom-uniphy.h | 33 ++
1 file changed, 33 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy.h
b/drivers/phy
Port Qualcomm QMP HDMI PHY to the generic PHY framework. Split the
generic part and the msm8996 part. When adding support for msm8992/4 and
msm8998 (which also employ QMP for HDMI PHY), one will have to provide
the PLL programming part only.
Signed-off-by: Dmitry Baryshkov
---
drivers/phy/qualco
From: Sandor Yu
Allow HDMI PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The parameters added here are based on HDMI PHY
implementation practices. The current set of parameters
should cover the potential users.
Signed-off-by: Sandor
The MSM HDMI PHYs have been using the ad-hoc approach / API instead of
using the generic API framework. Move all the PHYs to
drivers/phy/qualcomm and rework them to use generic PHY framework. This
way all the QMP-related code is kept close. Also in future this will
allow us to use a common set of f
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